verilator/test_regress/t/t_class_ref_ref.v

24 lines
385 B
Systemverilog
Raw Normal View History

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2024 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
2026-03-08 23:26:40 +01:00
class Cls #(
type T = bit
);
endclass
module t;
2026-03-08 23:26:40 +01:00
Cls #(bit) cb;
2026-03-08 23:26:40 +01:00
Cls #(Cls #(bit)) ccb;
2026-03-08 23:26:40 +01:00
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule