2023-04-20 00:05:37 +02:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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2023-04-20 00:05:37 +02:00
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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endclass
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2026-03-08 23:26:40 +01:00
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class Bar #(
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type BASE = Foo
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) extends BASE;
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2023-04-20 00:05:37 +02:00
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task body();
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int v = 0;
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v = 1;
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endtask
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endclass
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