2015-10-24 00:13:25 +02:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2015 Johan Bjork
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2020-03-21 16:24:24 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2015-10-24 00:13:25 +02:00
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module t;
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2026-03-03 13:21:24 +01:00
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localparam STR = "string";
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function logic checkParameter(input logic [8:0] N);
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$info("For %m, x is %d.", N);
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if (N == 1) return 0;
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$fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work");
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endfunction
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2015-10-24 00:13:25 +02:00
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`ifdef FAILING_ASSERTIONS
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2026-03-03 13:21:24 +01:00
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localparam X = checkParameter(5);
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2015-10-24 00:13:25 +02:00
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`else
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2026-03-03 13:21:24 +01:00
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localparam X = checkParameter(1);
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2015-10-24 00:13:25 +02:00
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`endif
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2026-03-03 13:21:24 +01:00
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generate
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$info("%m: In generate"); // Issue 6445
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endgenerate
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2025-09-17 02:48:23 +02:00
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2026-03-03 13:21:24 +01:00
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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2015-10-24 00:13:25 +02:00
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endmodule
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