Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Emit C++ for model entry point class
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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2023-01-01 16:18:39 +01:00
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// Copyright 2003-2023 by Wilson Snyder. This program is free software; you
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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#include "config_build.h"
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#include "verilatedos.h"
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#include "V3EmitC.h"
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#include "V3EmitCFunc.h"
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2022-08-05 11:56:57 +02:00
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#include "V3Global.h"
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2021-07-14 23:37:37 +02:00
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#include "V3UniqueNames.h"
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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#include <algorithm>
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2021-11-27 23:07:27 +01:00
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#include <functional>
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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#include <vector>
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2022-09-18 21:53:42 +02:00
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VL_DEFINE_DEBUG_FUNCTIONS;
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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class EmitCModel final : public EmitCFunc {
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2021-11-27 23:07:27 +01:00
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// TYPES
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using CFuncVector = std::vector<const AstCFunc*>;
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// MEMBERS
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2021-07-14 23:37:37 +02:00
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V3UniqueNames m_uniqueNames; // For generating unique file names
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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// METHODS
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2021-11-27 23:07:27 +01:00
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CFuncVector findFuncps(std::function<bool(const AstCFunc*)> cb) {
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CFuncVector funcps;
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for (AstNode* nodep = m_modp->stmtsp(); nodep; nodep = nodep->nextp()) {
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if (const AstCFunc* const funcp = VN_CAST(nodep, CFunc)) {
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if (cb(funcp)) funcps.push_back(funcp);
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}
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}
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stable_sort(funcps.begin(), funcps.end(),
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[](const AstNode* ap, const AstNode* bp) { return ap->name() < bp->name(); });
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return funcps;
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}
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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void putSectionDelimiter(const string& name) {
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puts("\n");
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puts("//============================================================\n");
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puts("// " + name + "\n");
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}
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void emitHeader(AstNodeModule* modp) {
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UASSERT(!m_ofp, "Output file should not be open");
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const string filename = v3Global.opt.makeDir() + "/" + topClassName() + ".h";
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newCFile(filename, /* slow: */ false, /* source: */ false);
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2022-11-20 19:11:01 +01:00
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m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename};
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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ofp()->putsHeader();
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puts("// DESCRIPTION: Verilator output: Primary model header\n");
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puts("//\n");
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puts("// This header should be included by all source files instantiating the design.\n");
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puts("// The class here is then constructed to instantiate the design.\n");
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puts("// See the Verilator manual for examples.\n");
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ofp()->putsGuard();
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// Include files
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puts("\n");
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ofp()->putsIntTopInclude();
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2021-07-24 16:00:33 +02:00
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puts("#include \"verilated.h\"\n");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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if (v3Global.opt.mtasks()) puts("#include \"verilated_threads.h\"\n");
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if (v3Global.opt.savable()) puts("#include \"verilated_save.h\"\n");
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if (v3Global.opt.coverage()) puts("#include \"verilated_cov.h\"\n");
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if (v3Global.dpi()) puts("#include \"svdpi.h\"\n");
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// Declare foreign instances up front to make C++ happy
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puts("\n");
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puts("class " + symClassName() + ";\n");
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puts("class " + prefixNameProtect(modp) + ";\n"); // For rootp pointer only
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if (v3Global.opt.trace()) puts("class " + v3Global.opt.traceClassLang() + ";\n");
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emitModCUse(modp, VUseType::INT_FWD_CLASS); // Note: This is needed for cell forwarding
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puts("\n");
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puts("// This class is the main interface to the Verilated model\n");
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2023-05-03 03:21:10 +02:00
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puts("class alignas(VL_CACHE_LINE_BYTES) " + topClassName() + " VL_NOT_FINAL : ");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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if (optSystemC()) {
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2022-07-12 12:41:15 +02:00
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// SC_MODULE, but with multiple-inheritance of VerilatedModel
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puts("public ::sc_core::sc_module, ");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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2022-07-12 12:41:15 +02:00
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puts("public VerilatedModel {\n");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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ofp()->resetPrivate();
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ofp()->putsPrivate(true); // private:
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puts("// Symbol table holding complete model state (owned by this class)\n");
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puts(symClassName() + "* const vlSymsp;\n");
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puts("\n");
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ofp()->putsPrivate(false); // public:
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// User accessible IO
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puts("\n// PORTS\n"
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"// The application code writes and reads these signals to\n"
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"// propagate new values into/out from the Verilated model.\n");
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for (const AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
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2021-10-22 16:15:42 +02:00
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if (const AstVar* const varp = VN_CAST(nodep, Var)) {
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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if (varp->isPrimaryIO()) { //
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Add V3VariableOrder pass
A separate V3VariableOrder pass is now used to order module variables
before Emit. All variables are now ordered together, without
consideration for whether they are ports, signals form the design, or
additional internal variables added by Verilator (which used to be
ordered and emitted as separate groups in Emit). For single threaded
models, this is performance neutral. For multi-threaded models, the
MTask affinity based sorting was slightly modified, so variables with no
MTask affinity are emitted last, otherwise the MTask affinity sets are
sorted using the TSP sorter as before, but again, ports, signals, and
internal variables are not differentiated. This yields a 2%+ speedup for
the multithreaded model on OpenTitan.
2021-06-29 18:57:07 +02:00
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emitVarDecl(varp, /* asRef: */ true);
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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}
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}
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Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
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if (optSystemC() && v3Global.usesTiming()) puts("sc_event trigger_eval;\n");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
// Cells instantiated by the top level (for access to /* verilator public */)
|
|
|
|
|
puts("\n// CELLS\n"
|
|
|
|
|
"// Public to allow access to /* verilator public */ items.\n"
|
|
|
|
|
"// Otherwise the application code can consider these internals.\n");
|
|
|
|
|
for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
2021-10-22 16:15:42 +02:00
|
|
|
if (const AstCell* const cellp = VN_CAST(nodep, Cell)) {
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts(prefixNameProtect(cellp->modp()) + "* const " + cellp->nameProtect() + ";\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// root instance pointer (for access to internals, including public_flat items).
|
|
|
|
|
puts("\n// Root instance pointer to allow access to model internals,\n"
|
|
|
|
|
"// including inlined /* verilator public_flat_* */ items.\n");
|
|
|
|
|
puts(prefixNameProtect(modp) + "* const rootp;\n");
|
|
|
|
|
|
|
|
|
|
puts("\n");
|
|
|
|
|
ofp()->putsPrivate(false); // public:
|
|
|
|
|
puts("// CONSTRUCTORS\n");
|
|
|
|
|
if (optSystemC()) {
|
|
|
|
|
puts("SC_CTOR(" + topClassName() + ");\n");
|
|
|
|
|
puts("virtual ~" + topClassName() + "();\n");
|
|
|
|
|
} else {
|
|
|
|
|
puts("/// Construct the model; called by application code\n");
|
|
|
|
|
puts("/// If contextp is null, then the model will use the default global "
|
|
|
|
|
"context\n");
|
|
|
|
|
puts("/// If name is \"\", then makes a wrapper with a\n");
|
|
|
|
|
puts("/// single model invisible with respect to DPI scope names.\n");
|
|
|
|
|
puts("explicit " + topClassName() + "(VerilatedContext* contextp,"
|
|
|
|
|
+ " const char* name = \"TOP\");\n");
|
|
|
|
|
puts("explicit " + topClassName() + "(const char* name = \"TOP\");\n");
|
|
|
|
|
puts("/// Destroy the model; called (often implicitly) by application code\n");
|
|
|
|
|
puts("virtual ~" + topClassName() + "();\n");
|
|
|
|
|
}
|
|
|
|
|
ofp()->putsPrivate(true);
|
|
|
|
|
puts("VL_UNCOPYABLE(" + topClassName() + "); ///< Copying not allowed\n");
|
|
|
|
|
|
|
|
|
|
puts("\n");
|
|
|
|
|
ofp()->putsPrivate(false); // public:
|
|
|
|
|
puts("// API METHODS\n");
|
2021-11-26 23:55:36 +01:00
|
|
|
const string callEvalEndStep
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
= (v3Global.needTraceDumper() && !optSystemC()) ? "eval_end_step(); " : "";
|
|
|
|
|
if (optSystemC()) {
|
|
|
|
|
ofp()->putsPrivate(true); ///< eval() is invoked by our sensitive() calls.
|
|
|
|
|
}
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Evaluate the model. Application must call when inputs change.\n");
|
|
|
|
|
}
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
if (optSystemC() && v3Global.usesTiming()) {
|
|
|
|
|
puts("void eval();\n");
|
|
|
|
|
puts("void eval_sens();\n");
|
|
|
|
|
} else {
|
|
|
|
|
puts("void eval() { eval_step(); " + callEvalEndStep + "}\n");
|
|
|
|
|
}
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Evaluate when calling multiple units/models per time step.\n");
|
|
|
|
|
}
|
|
|
|
|
puts("void eval_step();\n");
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Evaluate at end of a timestep for tracing, when using eval_step().\n");
|
|
|
|
|
puts("/// Application must call after all eval() and before time changes.\n");
|
|
|
|
|
puts("void eval_end_step()");
|
|
|
|
|
if (callEvalEndStep == "") {
|
|
|
|
|
puts(" {}\n");
|
|
|
|
|
} else {
|
|
|
|
|
puts(";\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Simulation complete, run final blocks. Application "
|
|
|
|
|
"must call on completion.\n");
|
|
|
|
|
}
|
|
|
|
|
ofp()->putsPrivate(false); // public:
|
|
|
|
|
puts("void final();\n");
|
|
|
|
|
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
puts("/// Are there scheduled events to handle?\n");
|
|
|
|
|
puts("bool eventsPending();\n");
|
|
|
|
|
puts("/// Returns time at next time slot. Aborts if !eventsPending()\n");
|
|
|
|
|
puts("uint64_t nextTimeSlot();\n");
|
|
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (v3Global.opt.trace()) {
|
|
|
|
|
puts("/// Trace signals in the model; called by application code\n");
|
|
|
|
|
puts("void trace(" + v3Global.opt.traceClassBase()
|
|
|
|
|
+ "C* tfp, int levels, int options = 0);\n");
|
|
|
|
|
if (optSystemC()) {
|
|
|
|
|
puts("/// SC tracing; avoid overloaded virtual function lint warning\n");
|
2022-09-16 12:22:11 +02:00
|
|
|
puts("void trace(sc_trace_file* tfp) const override { "
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
"::sc_core::sc_module::trace(tfp); }\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Retrieve name of this model instance (as passed to constructor).\n");
|
|
|
|
|
puts("const char* name() const;\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Emit DPI export dispatcher declarations
|
|
|
|
|
{
|
2021-11-27 23:07:27 +01:00
|
|
|
const CFuncVector funcps
|
|
|
|
|
= findFuncps([](const AstCFunc* nodep) { return nodep->dpiExportDispatcher(); });
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (!funcps.empty()) {
|
|
|
|
|
puts("\n/// DPI Export functions\n");
|
2021-11-27 23:07:27 +01:00
|
|
|
for (const AstCFunc* funcp : funcps) emitCFuncDecl(funcp, modp);
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (v3Global.opt.savable()) {
|
|
|
|
|
puts("\n");
|
|
|
|
|
puts("// Serialization functions\n");
|
|
|
|
|
puts("friend VerilatedSerialize& operator<<(VerilatedSerialize& os, " //
|
|
|
|
|
+ topClassName() + "& rhs);\n");
|
|
|
|
|
puts("friend VerilatedDeserialize& operator>>(VerilatedDeserialize& os, "
|
|
|
|
|
+ topClassName() + "& rhs);\n");
|
|
|
|
|
}
|
|
|
|
|
|
2022-07-12 12:41:15 +02:00
|
|
|
puts("\n// Abstract methods from VerilatedModel\n");
|
2022-07-12 16:50:11 +02:00
|
|
|
puts("const char* hierName() const override final;\n");
|
|
|
|
|
puts("const char* modelName() const override final;\n");
|
|
|
|
|
puts("unsigned threads() const override final;\n");
|
2023-08-30 13:02:55 +02:00
|
|
|
puts("/// Prepare for cloning the model at the process level (e.g. fork in Linux)\n");
|
|
|
|
|
puts("/// Release necessary resources. Called before cloning.\n");
|
|
|
|
|
puts("void prepareClone() const;\n");
|
|
|
|
|
puts("/// Re-init after cloning the model at the process level (e.g. fork in Linux)\n");
|
|
|
|
|
puts("/// Re-allocate necessary resources. Called after cloning.\n");
|
|
|
|
|
puts("void atClone() const;\n");
|
2022-07-20 12:27:10 +02:00
|
|
|
if (v3Global.opt.trace()) {
|
|
|
|
|
puts("std::unique_ptr<VerilatedTraceConfig> traceConfig() const override final;\n");
|
|
|
|
|
}
|
2022-07-12 12:41:15 +02:00
|
|
|
|
2023-05-03 03:21:10 +02:00
|
|
|
puts("};\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
ofp()->putsEndGuard();
|
|
|
|
|
|
|
|
|
|
VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitConstructorImplementation(AstNodeModule* modp) {
|
|
|
|
|
putSectionDelimiter("Constructors");
|
|
|
|
|
|
|
|
|
|
puts("\n");
|
|
|
|
|
puts(topClassName() + "::" + topClassName());
|
|
|
|
|
if (optSystemC()) {
|
|
|
|
|
puts("(sc_module_name /* unused */)\n");
|
2022-07-12 16:38:24 +02:00
|
|
|
puts(" : VerilatedModel{*Verilated::threadContextp()}\n");
|
|
|
|
|
puts(" , vlSymsp{new " + symClassName() + "(contextp(), name(), this)}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
} else {
|
|
|
|
|
puts(+"(VerilatedContext* _vcontextp__, const char* _vcname__)\n");
|
2022-07-12 16:38:24 +02:00
|
|
|
puts(" : VerilatedModel{*_vcontextp__}\n");
|
|
|
|
|
puts(" , vlSymsp{new " + symClassName() + "(contextp(), _vcname__, this)}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Set up IO references
|
|
|
|
|
for (const AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
2021-10-22 16:15:42 +02:00
|
|
|
if (const AstVar* const varp = VN_CAST(nodep, Var)) {
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (varp->isPrimaryIO()) {
|
|
|
|
|
const string protName = varp->nameProtect();
|
|
|
|
|
puts(" , " + protName + "{vlSymsp->TOP." + protName + "}\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Setup cell pointers
|
|
|
|
|
for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
2021-10-22 16:15:42 +02:00
|
|
|
if (const AstCell* const cellp = VN_CAST(nodep, Cell)) {
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
const string protName = cellp->nameProtect();
|
|
|
|
|
puts(" , " + protName + "{vlSymsp->TOP." + protName + "}\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Setup rootp root instance pointer,
|
|
|
|
|
puts(" , rootp{&(vlSymsp->TOP)}\n");
|
|
|
|
|
|
|
|
|
|
puts("{\n");
|
2022-07-12 12:41:15 +02:00
|
|
|
puts("// Register model with the context\n");
|
2022-07-12 16:38:24 +02:00
|
|
|
puts("contextp()->addModel(this);\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
if (optSystemC()) {
|
|
|
|
|
// Create sensitivity list for when to evaluate the model.
|
|
|
|
|
putsDecoration("// Sensitivities on all clocks and combinational inputs\n");
|
|
|
|
|
puts("SC_METHOD(eval);\n");
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
if (v3Global.usesTiming()) puts("SC_METHOD(eval_sens);\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
|
|
|
|
if (const AstVar* const varp = VN_CAST(nodep, Var)) {
|
|
|
|
|
if (varp->isNonOutput() && (varp->isScSensitive() || varp->isUsedClock())) {
|
|
|
|
|
int vects = 0;
|
|
|
|
|
// This isn't very robust and may need cleanup for other data types
|
|
|
|
|
for (AstUnpackArrayDType* arrayp
|
|
|
|
|
= VN_CAST(varp->dtypeSkipRefp(), UnpackArrayDType);
|
|
|
|
|
arrayp;
|
|
|
|
|
arrayp = VN_CAST(arrayp->subDTypep()->skipRefp(), UnpackArrayDType)) {
|
|
|
|
|
const int vecnum = vects++;
|
|
|
|
|
UASSERT_OBJ(arrayp->hi() >= arrayp->lo(), varp,
|
|
|
|
|
"Should have swapped msb & lsb earlier.");
|
2021-07-23 02:05:54 +02:00
|
|
|
const string ivar = std::string{"__Vi"} + cvtToStr(vecnum);
|
2022-10-16 00:47:10 +02:00
|
|
|
puts("for (int __Vi" + cvtToStr(vecnum) + " = "
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
+ cvtToStr(arrayp->lo()));
|
2022-10-16 00:47:10 +02:00
|
|
|
puts("; " + ivar + " <= " + cvtToStr(arrayp->hi()));
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("; ++" + ivar + ") {\n");
|
|
|
|
|
}
|
|
|
|
|
puts("sensitive << " + varp->nameProtect());
|
|
|
|
|
for (int v = 0; v < vects; ++v) puts("[__Vi" + cvtToStr(v) + "]");
|
|
|
|
|
puts(";\n");
|
|
|
|
|
for (int v = 0; v < vects; ++v) puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
puts("\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
puts("}\n");
|
|
|
|
|
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("\n");
|
|
|
|
|
puts(topClassName() + "::" + topClassName() + "(const char* _vcname__)\n");
|
2022-07-12 12:41:15 +02:00
|
|
|
puts(" : " + topClassName() + "(Verilated::threadContextp(), _vcname__)\n{\n}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitDestructorImplementation() {
|
|
|
|
|
putSectionDelimiter("Destructor");
|
|
|
|
|
|
|
|
|
|
puts("\n");
|
|
|
|
|
puts(topClassName() + "::~" + topClassName() + "() {\n");
|
|
|
|
|
puts("delete vlSymsp;\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
2021-09-24 04:59:36 +02:00
|
|
|
void emitStandardMethods1(AstNodeModule* modp) {
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
UASSERT_OBJ(modp->isTop(), modp, "Attempting to emitWrapEval for non-top class");
|
|
|
|
|
|
|
|
|
|
const string topModNameProtected = prefixNameProtect(modp);
|
|
|
|
|
const string selfDecl = "(" + topModNameProtected + "* vlSelf)";
|
|
|
|
|
|
2022-05-15 17:03:32 +02:00
|
|
|
putSectionDelimiter("Evaluation function");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
// Forward declarations
|
|
|
|
|
puts("\n");
|
|
|
|
|
puts("#ifdef VL_DEBUG\n");
|
|
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval_debug_assertions") + selfDecl
|
|
|
|
|
+ ";\n");
|
|
|
|
|
puts("#endif // VL_DEBUG\n");
|
2022-05-15 17:03:32 +02:00
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval_static") + selfDecl + ";\n");
|
|
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval_initial") + selfDecl + ";\n");
|
|
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval_settle") + selfDecl + ";\n");
|
|
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval") + selfDecl + ";\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
if (optSystemC() && v3Global.usesTiming()) {
|
|
|
|
|
// ::eval
|
|
|
|
|
puts("\nvoid " + topClassName() + "::eval() {\n");
|
|
|
|
|
puts("eval_step();\n");
|
|
|
|
|
puts("if (eventsPending()) {\n");
|
|
|
|
|
puts("sc_time dt = sc_time::from_value(nextTimeSlot() - contextp()->time());\n");
|
|
|
|
|
puts("next_trigger(dt, trigger_eval);\n");
|
|
|
|
|
puts("} else {\n");
|
|
|
|
|
puts("next_trigger(trigger_eval);\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
|
|
|
|
|
// ::eval_sens
|
|
|
|
|
puts("\nvoid " + topClassName() + "::eval_sens() {\n");
|
|
|
|
|
puts("trigger_eval.notify();\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
// ::eval_step
|
|
|
|
|
puts("\nvoid " + topClassName() + "::eval_step() {\n");
|
|
|
|
|
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+++++TOP Evaluate " + topClassName()
|
|
|
|
|
+ "::eval_step\\n\"); );\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("#ifdef VL_DEBUG\n");
|
|
|
|
|
putsDecoration("// Debug assertions\n");
|
|
|
|
|
puts(topModNameProtected + "__" + protect("_eval_debug_assertions")
|
|
|
|
|
+ "(&(vlSymsp->TOP));\n");
|
|
|
|
|
puts("#endif // VL_DEBUG\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
|
2022-05-15 17:03:32 +02:00
|
|
|
if (v3Global.opt.trace()) puts("vlSymsp->__Vm_activity = true;\n");
|
|
|
|
|
|
|
|
|
|
if (v3Global.hasEvents()) puts("vlSymsp->clearTriggeredEvents();\n");
|
2022-09-29 00:54:18 +02:00
|
|
|
if (v3Global.hasClasses()) puts("vlSymsp->__Vm_deleter.deleteAll();\n");
|
2022-05-15 17:03:32 +02:00
|
|
|
|
|
|
|
|
puts("if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {\n");
|
|
|
|
|
puts("vlSymsp->__Vm_didInit = true;\n");
|
|
|
|
|
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+ Initial\\n\"););\n");
|
|
|
|
|
puts(topModNameProtected + "__" + protect("_eval_static") + "(&(vlSymsp->TOP));\n");
|
|
|
|
|
puts(topModNameProtected + "__" + protect("_eval_initial") + "(&(vlSymsp->TOP));\n");
|
|
|
|
|
puts(topModNameProtected + "__" + protect("_eval_settle") + "(&(vlSymsp->TOP));\n");
|
|
|
|
|
puts("}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
if (v3Global.opt.threads() == 1) {
|
2021-11-26 23:55:36 +01:00
|
|
|
const uint32_t mtaskId = 0;
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
putsDecoration("// MTask " + cvtToStr(mtaskId) + " start\n");
|
|
|
|
|
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"MTask" + cvtToStr(mtaskId) + " starting\\n\"););\n");
|
|
|
|
|
puts("Verilated::mtaskId(" + cvtToStr(mtaskId) + ");\n");
|
|
|
|
|
}
|
|
|
|
|
|
2022-03-25 20:46:50 +01:00
|
|
|
if (v3Global.opt.profExec()) {
|
2022-07-12 12:41:15 +02:00
|
|
|
puts("vlSymsp->__Vm_executionProfilerp->configure();\n");
|
2022-03-25 20:46:50 +01:00
|
|
|
puts("VL_EXEC_TRACE_ADD_RECORD(vlSymsp).evalBegin();\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
}
|
|
|
|
|
|
2022-05-15 17:03:32 +02:00
|
|
|
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+ Eval\\n\"););\n");
|
|
|
|
|
puts(topModNameProtected + "__" + protect("_eval") + "(&(vlSymsp->TOP));\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
|
|
|
|
|
putsDecoration("// Evaluate cleanup\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (v3Global.opt.threads() == 1) {
|
|
|
|
|
puts("Verilated::endOfThreadMTask(vlSymsp->__Vm_evalMsgQp);\n");
|
|
|
|
|
}
|
|
|
|
|
if (v3Global.opt.threads()) puts("Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
|
2022-03-25 20:46:50 +01:00
|
|
|
if (v3Global.opt.profExec()) puts("VL_EXEC_TRACE_ADD_RECORD(vlSymsp).evalEnd();\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("}\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
}
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
2022-05-15 17:03:32 +02:00
|
|
|
void emitStandardMethods2(AstNodeModule* modp) {
|
2021-09-24 04:59:36 +02:00
|
|
|
const string topModNameProtected = prefixNameProtect(modp);
|
2022-05-15 17:03:32 +02:00
|
|
|
const string selfDecl = "(" + topModNameProtected + "* vlSelf)";
|
|
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
// ::eval_end_step
|
|
|
|
|
if (v3Global.needTraceDumper() && !optSystemC()) {
|
|
|
|
|
puts("\nvoid " + topClassName() + "::eval_end_step() {\n");
|
|
|
|
|
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+eval_end_step " + topClassName()
|
|
|
|
|
+ "::eval_end_step\\n\"); );\n");
|
|
|
|
|
puts("#ifdef VM_TRACE\n");
|
|
|
|
|
putsDecoration("// Tracing\n");
|
|
|
|
|
// SystemC's eval loop deals with calling trace, not us
|
|
|
|
|
puts("if (VL_UNLIKELY(vlSymsp->__Vm_dumping)) vlSymsp->_traceDump();\n");
|
|
|
|
|
puts("#endif // VM_TRACE\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
2022-10-06 00:16:05 +02:00
|
|
|
putSectionDelimiter("Events and timing");
|
|
|
|
|
if (auto* const delaySchedp = v3Global.rootp()->delaySchedulerp()) {
|
|
|
|
|
puts("bool " + topClassName() + "::eventsPending() { return !vlSymsp->TOP.");
|
|
|
|
|
puts(delaySchedp->nameProtect());
|
|
|
|
|
puts(".empty(); }\n\n");
|
|
|
|
|
puts("uint64_t " + topClassName() + "::nextTimeSlot() { return vlSymsp->TOP.");
|
|
|
|
|
puts(delaySchedp->nameProtect());
|
|
|
|
|
puts(".nextTimeSlot(); }\n");
|
|
|
|
|
} else {
|
|
|
|
|
puts("bool " + topClassName() + "::eventsPending() { return false; }\n\n");
|
|
|
|
|
puts("uint64_t " + topClassName() + "::nextTimeSlot() {\n");
|
|
|
|
|
puts("VL_FATAL_MT(__FILE__, __LINE__, \"\", \"%Error: No delays in the "
|
|
|
|
|
"design\");\n");
|
|
|
|
|
puts("return 0;\n}\n");
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
}
|
|
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
putSectionDelimiter("Utilities");
|
|
|
|
|
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
// ::name
|
|
|
|
|
puts("\nconst char* " + topClassName() + "::name() const {\n");
|
|
|
|
|
puts(/**/ "return vlSymsp->name();\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
}
|
2021-11-14 17:05:20 +01:00
|
|
|
|
|
|
|
|
putSectionDelimiter("Invoke final blocks");
|
2022-05-15 17:03:32 +02:00
|
|
|
// Forward declarations
|
|
|
|
|
puts("\n");
|
|
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval_final") + selfDecl + ";\n");
|
2021-11-14 17:05:20 +01:00
|
|
|
// ::final
|
|
|
|
|
puts("\nVL_ATTR_COLD void " + topClassName() + "::final() {\n");
|
2022-05-15 17:03:32 +02:00
|
|
|
puts(/**/ topModNameProtected + "__" + protect("_eval_final") + "(&(vlSymsp->TOP));\n");
|
2021-11-14 17:05:20 +01:00
|
|
|
puts("}\n");
|
2022-07-12 12:41:15 +02:00
|
|
|
|
|
|
|
|
putSectionDelimiter("Implementations of abstract methods from VerilatedModel\n");
|
2022-07-12 16:50:11 +02:00
|
|
|
puts("const char* " + topClassName() + "::hierName() const { return vlSymsp->name(); }\n");
|
|
|
|
|
puts("const char* " + topClassName() + "::modelName() const { return \"" + topClassName()
|
2022-07-12 12:41:15 +02:00
|
|
|
+ "\"; }\n");
|
2022-07-12 16:50:11 +02:00
|
|
|
puts("unsigned " + topClassName() + "::threads() const { return "
|
2022-07-12 12:41:15 +02:00
|
|
|
+ cvtToStr(std::max(1, v3Global.opt.threads())) + "; }\n");
|
2023-08-30 13:02:55 +02:00
|
|
|
puts("void " + topClassName()
|
|
|
|
|
+ "::prepareClone() const { contextp()->prepareClone(); }\n");
|
|
|
|
|
puts("void " + topClassName() + "::atClone() const {\n");
|
|
|
|
|
if (v3Global.opt.threads() > 1) {
|
|
|
|
|
puts("vlSymsp->__Vm_threadPoolp = static_cast<VlThreadPool*>(");
|
|
|
|
|
}
|
|
|
|
|
puts("contextp()->threadPoolpOnClone()");
|
|
|
|
|
if (v3Global.opt.threads() > 1) puts(")");
|
|
|
|
|
puts(";\n}\n");
|
2022-07-20 12:27:10 +02:00
|
|
|
|
|
|
|
|
if (v3Global.opt.trace()) {
|
|
|
|
|
puts("std::unique_ptr<VerilatedTraceConfig> " + topClassName()
|
|
|
|
|
+ "::traceConfig() const {\n");
|
|
|
|
|
puts("return std::unique_ptr<VerilatedTraceConfig>{new VerilatedTraceConfig{");
|
|
|
|
|
puts(v3Global.opt.useTraceParallel() ? "true" : "false");
|
|
|
|
|
puts(v3Global.opt.useTraceOffload() ? ", true" : ", false");
|
|
|
|
|
puts(v3Global.opt.useFstWriterThread() ? ", true" : ", false");
|
|
|
|
|
puts("}};\n");
|
|
|
|
|
puts("};\n");
|
|
|
|
|
}
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitTraceMethods(AstNodeModule* modp) {
|
|
|
|
|
const string topModNameProtected = prefixNameProtect(modp);
|
|
|
|
|
|
|
|
|
|
putSectionDelimiter("Trace configuration");
|
|
|
|
|
|
|
|
|
|
// Forward declaration
|
2021-06-22 14:16:23 +02:00
|
|
|
puts("\nvoid " + topModNameProtected + "__" + protect("trace_init_top") + "("
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
+ topModNameProtected + "* vlSelf, " + v3Global.opt.traceClassBase()
|
|
|
|
|
+ "* tracep);\n");
|
|
|
|
|
|
|
|
|
|
// Static helper function
|
2021-11-14 17:05:20 +01:00
|
|
|
puts("\nVL_ATTR_COLD static void " + protect("trace_init") + "(void* voidSelf, "
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
+ v3Global.opt.traceClassBase() + "* tracep, uint32_t code) {\n");
|
|
|
|
|
putsDecoration("// Callback from tracep->open()\n");
|
|
|
|
|
puts(voidSelfAssign(modp));
|
|
|
|
|
puts(symClassAssign());
|
|
|
|
|
puts("if (!vlSymsp->_vm_contextp__->calcUnusedSigs()) {\n");
|
|
|
|
|
puts("VL_FATAL_MT(__FILE__, __LINE__, __FILE__,\n");
|
|
|
|
|
puts("\"Turning on wave traces requires Verilated::traceEverOn(true) call before time "
|
|
|
|
|
"0.\");\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
puts("vlSymsp->__Vm_baseCode = code;\n");
|
|
|
|
|
puts("tracep->scopeEscape(' ');\n");
|
2021-12-19 16:15:07 +01:00
|
|
|
puts("tracep->pushNamePrefix(std::string{vlSymsp->name()} + ' ');\n");
|
2021-06-22 14:16:23 +02:00
|
|
|
puts(topModNameProtected + "__" + protect("trace_init_top") + "(vlSelf, tracep);\n");
|
2021-12-19 16:15:07 +01:00
|
|
|
puts("tracep->popNamePrefix();\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("tracep->scopeEscape('.');\n"); // Restore so later traced files won't break
|
|
|
|
|
puts("}\n");
|
|
|
|
|
|
|
|
|
|
// Forward declaration
|
2021-11-14 18:01:02 +01:00
|
|
|
puts("\nVL_ATTR_COLD void " + topModNameProtected + "__" + protect("trace_register") + "("
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
+ topModNameProtected + "* vlSelf, " + v3Global.opt.traceClassBase()
|
|
|
|
|
+ "* tracep);\n");
|
|
|
|
|
|
2021-11-27 23:07:27 +01:00
|
|
|
const CFuncVector traceInitFuncps
|
|
|
|
|
= findFuncps([](const AstCFunc* nodep) { return nodep->dpiTraceInit(); });
|
|
|
|
|
for (const AstCFunc* const funcp : traceInitFuncps) emitCFuncDecl(funcp, modp);
|
|
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
// ::trace
|
2021-11-14 17:05:20 +01:00
|
|
|
puts("\nVL_ATTR_COLD void " + topClassName() + "::trace(");
|
2021-11-27 23:07:27 +01:00
|
|
|
puts(v3Global.opt.traceClassBase() + "C* tfp, int levels, int options) {\n");
|
2021-12-23 00:41:11 +01:00
|
|
|
if (optSystemC()) {
|
|
|
|
|
puts(/**/ "if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {\n");
|
|
|
|
|
puts(/****/ "vl_fatal(__FILE__, __LINE__, name(), \"" + topClassName()
|
|
|
|
|
+ +"::trace() is called before sc_core::sc_start(). "
|
|
|
|
|
"Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before trace() to complete "
|
|
|
|
|
"elaboration.\");\n");
|
|
|
|
|
puts(/**/ "}");
|
|
|
|
|
}
|
2022-09-20 22:45:09 +02:00
|
|
|
puts(/**/ "if (tfp->isOpen()) {\n");
|
|
|
|
|
puts(/****/ "vl_fatal(__FILE__, __LINE__, __FILE__,\"'" + topClassName()
|
|
|
|
|
+ +"::trace()' shall not be called after '" + v3Global.opt.traceClassBase()
|
|
|
|
|
+ "C::open()'.\");\n");
|
|
|
|
|
puts(/**/ "}\n");
|
2021-11-27 23:07:27 +01:00
|
|
|
puts(/**/ "if (false && levels && options) {} // Prevent unused\n");
|
2022-07-20 12:27:10 +02:00
|
|
|
puts(/**/ "tfp->spTrace()->addModel(this);\n");
|
|
|
|
|
puts(/**/ "tfp->spTrace()->addInitCb(&" + protect("trace_init") + ", &(vlSymsp->TOP));\n");
|
2021-11-14 18:01:02 +01:00
|
|
|
puts(/**/ topModNameProtected + "__" + protect("trace_register")
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
+ "(&(vlSymsp->TOP), tfp->spTrace());\n");
|
2021-11-27 23:07:27 +01:00
|
|
|
|
|
|
|
|
if (!traceInitFuncps.empty()) {
|
|
|
|
|
puts(/**/ "if (levels > 0) {\n");
|
|
|
|
|
puts(/****/ "const QData tfpq = reinterpret_cast<QData>(tfp);\n");
|
|
|
|
|
for (const AstCFunc* const funcp : traceInitFuncps) {
|
|
|
|
|
// Some hackery to locate handle__V for trace_init_task
|
|
|
|
|
// Considered a pragma on the handle, but that still doesn't help us attach it here
|
|
|
|
|
string handle = funcp->name();
|
2022-09-15 03:10:19 +02:00
|
|
|
const size_t wr_len = std::strlen("__Vdpiimwrap_");
|
2021-11-27 23:07:27 +01:00
|
|
|
UASSERT_OBJ(handle.substr(0, wr_len) == "__Vdpiimwrap_", funcp,
|
|
|
|
|
"Strange trace_init_task function name");
|
|
|
|
|
handle = "vlSymsp->TOP." + handle.substr(wr_len);
|
|
|
|
|
const string::size_type pos = handle.rfind("__DOT__");
|
|
|
|
|
UASSERT_OBJ(pos != string::npos, funcp, "Strange trace_init_task function name");
|
|
|
|
|
handle = handle.substr(0, pos) + "__DOT__handle___05FV";
|
|
|
|
|
puts(funcNameProtect(funcp, modp) + "(" + handle
|
|
|
|
|
+ ", tfpq, levels - 1, options);\n");
|
|
|
|
|
}
|
|
|
|
|
puts(/**/ "}\n");
|
|
|
|
|
}
|
|
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitSerializationFunctions() {
|
|
|
|
|
putSectionDelimiter("Model serialization");
|
|
|
|
|
|
|
|
|
|
puts("\nVerilatedSerialize& operator<<(VerilatedSerialize& os, " + topClassName()
|
|
|
|
|
+ "& rhs) {\n");
|
2021-11-14 18:01:02 +01:00
|
|
|
puts(/**/ "Verilated::quiesce();\n");
|
|
|
|
|
puts(/**/ "rhs.vlSymsp->" + protect("__Vserialize") + "(os);\n");
|
|
|
|
|
puts(/**/ "return os;\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("}\n");
|
|
|
|
|
|
|
|
|
|
puts("\nVerilatedDeserialize& operator>>(VerilatedDeserialize& os, " + topClassName()
|
|
|
|
|
+ "& rhs) {\n");
|
2021-11-14 18:01:02 +01:00
|
|
|
puts(/**/ "Verilated::quiesce();\n");
|
|
|
|
|
puts(/**/ "rhs.vlSymsp->" + protect("__Vdeserialize") + "(os);\n");
|
|
|
|
|
puts(/**/ "return os;\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitImplementation(AstNodeModule* modp) {
|
|
|
|
|
UASSERT(!m_ofp, "Output file should not be open");
|
|
|
|
|
|
|
|
|
|
const string filename = v3Global.opt.makeDir() + "/" + topClassName() + ".cpp";
|
|
|
|
|
newCFile(filename, /* slow: */ false, /* source: */ true);
|
2022-11-20 19:11:01 +01:00
|
|
|
m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename};
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
ofp()->putsHeader();
|
|
|
|
|
puts("// DESCRIPTION: Verilator output: "
|
|
|
|
|
"Model implementation (design independent parts)\n");
|
|
|
|
|
|
|
|
|
|
puts("\n");
|
|
|
|
|
puts("#include \"" + topClassName() + ".h\"\n");
|
|
|
|
|
puts("#include \"" + symClassName() + ".h\"\n");
|
|
|
|
|
if (v3Global.opt.trace()) {
|
|
|
|
|
puts("#include \"" + v3Global.opt.traceSourceLang() + ".h\"\n");
|
|
|
|
|
}
|
|
|
|
|
if (v3Global.dpi()) { //
|
|
|
|
|
puts("#include \"verilated_dpi.h\"\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
emitConstructorImplementation(modp);
|
|
|
|
|
emitDestructorImplementation();
|
2021-09-24 04:59:36 +02:00
|
|
|
emitStandardMethods1(modp);
|
|
|
|
|
emitStandardMethods2(modp);
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (v3Global.opt.trace()) { emitTraceMethods(modp); }
|
|
|
|
|
if (v3Global.opt.savable()) { emitSerializationFunctions(); }
|
|
|
|
|
|
|
|
|
|
VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitDpiExportDispatchers(AstNodeModule* modp) {
|
|
|
|
|
UASSERT(!m_ofp, "Output file should not be open");
|
|
|
|
|
|
|
|
|
|
// Emit DPI Export dispatchers
|
|
|
|
|
for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
|
|
|
|
AstCFunc* const funcp = VN_CAST(nodep, CFunc);
|
|
|
|
|
if (!funcp || !funcp->dpiExportDispatcher()) continue;
|
|
|
|
|
|
|
|
|
|
if (splitNeeded()) {
|
|
|
|
|
// Splitting file, so using parallel build.
|
|
|
|
|
v3Global.useParallelBuild(true);
|
|
|
|
|
// Close old file
|
|
|
|
|
VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!m_ofp) {
|
2021-07-14 23:37:37 +02:00
|
|
|
string filename = v3Global.opt.makeDir() + "/" + topClassName() + "__Dpi_Export";
|
|
|
|
|
filename = m_uniqueNames.get(filename);
|
|
|
|
|
filename += ".cpp";
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
newCFile(filename, /* slow: */ false, /* source: */ true);
|
2021-07-12 00:42:01 +02:00
|
|
|
m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename}
|
|
|
|
|
: new V3OutCFile{filename};
|
2021-07-14 23:37:37 +02:00
|
|
|
splitSizeReset(); // Reset file size tracking
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
m_lazyDecls.reset();
|
|
|
|
|
m_ofp->putsHeader();
|
|
|
|
|
puts(
|
|
|
|
|
"// DESCRIPTION: Verilator output: Implementation of DPI export functions.\n");
|
|
|
|
|
puts("//\n");
|
|
|
|
|
puts("#include \"" + topClassName() + ".h\"\n");
|
|
|
|
|
puts("#include \"" + symClassName() + ".h\"\n");
|
|
|
|
|
puts("#include \"verilated_dpi.h\"\n");
|
|
|
|
|
puts("\n");
|
|
|
|
|
}
|
|
|
|
|
|
2023-03-18 17:17:25 +01:00
|
|
|
iterateConst(funcp);
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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if (m_ofp) { VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); }
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}
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void main(AstNodeModule* modp) {
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m_modp = modp;
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emitHeader(modp);
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emitImplementation(modp);
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if (v3Global.dpi()) { emitDpiExportDispatchers(modp); }
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}
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// VISITORS
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public:
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explicit EmitCModel(AstNetlist* netlistp) { main(netlistp->topModulep()); }
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};
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//######################################################################
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// EmitC class functions
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void V3EmitC::emitcModel() {
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UINFO(2, __FUNCTION__ << ": " << endl);
|
2022-07-30 16:01:25 +02:00
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{ EmitCModel{v3Global.rootp()}; }
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|