26 lines
459 B
Systemverilog
26 lines
459 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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task take_ref(ref logic s);
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endtask
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endclass
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module t;
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logic a;
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logic b = 1;
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logic c;
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Cls cls = new;
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initial begin
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force a = b;
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cls.take_ref(c);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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