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#!/usr/bin/env python3
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2006-08-26 13:35:28 +02:00
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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2024-01-01 09:19:59 +01:00
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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2020-03-21 16:24:24 +01:00
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# can redistribute it and/or modify it under the terms of either the GNU
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2009-05-04 23:07:57 +02:00
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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2020-03-21 16:24:24 +01:00
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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2006-08-26 13:35:28 +02:00
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2024-09-08 19:00:03 +02:00
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import vltest_bootstrap
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2018-05-08 02:42:28 +02:00
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2024-09-08 19:00:03 +02:00
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test.scenarios('vlt')
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2006-08-26 13:35:28 +02:00
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Deprecate clocker attribute and --clk option (#6463)
The only use for the clocker attribute and the AstVar::isUsedClock that
is actually necessary today for correctness is to mark top level inputs
of --lib-create blocks as being (or driving) a clock signal. Correctness
of --lib-create (and hence hierarchical blocks) actually used to depend
on having the right optimizations eliminate intermediate clocks (e.g.:
V3Gate), when the top level port was not used directly in a sensitivity
list, or marking top level signals manually via --clk or the clocker
attribute. However V3Sched::partition already needs to trace through the
logic to figure out what signals might drive a sensitivity list, so it
can very easily mark all top level inputs as such.
In this patch we remove the AstVar::attrClocker and AstVar::isUsedClock
attributes, and replace them with AstVar::isPrimaryClock, automatically
set by V3Sched::partition. This eliminates all need for manual
annotation so we are deprecating the --clk/--no-clk options and the
clocker/no_clocker attributes.
This also eliminates the opportunity for any further mis-optimization
similar to #6453.
Regarding the other uses of the removed AstVar attributes:
- As of 5.000, initial edges are triggered via a separate mechanism
applied in V3Sched, so the use in V3EmitCFunc.cpp is redundant
- Also as of 5.000, we can handle arbitrary sensitivity expressions, so
the restriction on eliminating clock signals in V3Gate is unnecessary
- Since the recent change when Dfg is applied after V3Scope, it does
perform the equivalent of GateClkDecomp, so we can delete that pass.
2025-09-20 16:50:22 +02:00
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test.lint(verilator_flags2=["--trace-fst-thread --order-clock-delay --clk foo --no-clk bar"],
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fails=True,
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expect_filename=test.golden_filename)
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2006-08-26 13:35:28 +02:00
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test.passes()
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