30 lines
519 B
Systemverilog
30 lines
519 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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sub s ();
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assign s.a[0] = 0;
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assign s.b[1] = 1;
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initial begin
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if (s.a != 2) $stop;
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if (s.b != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub;
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wire [1:0] a, b;
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alias a = b;
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endmodule
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