2022-11-05 16:40:34 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Wilson Snyder
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2022-11-05 16:40:34 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2025-09-13 15:28:43 +02:00
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module t;
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2026-03-08 23:26:40 +01:00
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if ($test$plusargs("BAD-non-constant")) begin
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initial $stop;
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end
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case (1)
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$test$plusargs("BAD-non-constant"): initial $stop;
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endcase
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2022-11-05 16:40:34 +01:00
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endmodule
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