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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Wilson Snyder
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2020-03-21 16:24:24 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2025-09-13 15:28:43 +02:00
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module t;
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2026-03-08 23:26:40 +01:00
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wire [2:0] foo = 5'b11111;
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endmodule
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