verilator/test_regress/t/t_class_param_circ_bad.out

%Error: t/t_class_param_circ_bad.v:18:3: Exceeded maximum --module-recursion-depth of 100
                                       : ... note: In instance 't'
   18 |   ClsA #(PARAM + 1) a;
      |   ^~~~
        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to
Tests: Verilog format 2026-03-08 23:26:40 +01:00			`%Error: t/t_class_param_circ_bad.v:18:3: Exceeded maximum --module-recursion-depth of 100`
Cleanup some error messages to properly quote 2023-09-23 14:52:50 +02:00			`: ... note: In instance 't'`
Tests: Verilog format 2026-03-08 23:26:40 +01:00			`18 \| ClsA #(PARAM + 1) a;`
			`\| ^~~~`
Change error messages to more often suggest documentation 2025-04-05 23:10:28 +02:00			`... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.`
Fix memory leaks - batch 4 (#6439) 2025-09-16 20:22:36 +02:00			`%Error: Exiting due to`