2024-03-02 15:06:54 +01:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
|
|
|
// SPDX-FileCopyrightText: 2024 Wilson Snyder
|
2024-03-02 15:06:54 +01:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
class ClsDef;
|
2026-03-08 23:26:40 +01:00
|
|
|
int imembera;
|
|
|
|
|
function new(default);
|
|
|
|
|
imembera = i + 1;
|
|
|
|
|
endfunction
|
2024-03-02 15:06:54 +01:00
|
|
|
endclass
|
|
|
|
|
|
|
|
|
|
class ClsDefFwd;
|
2026-03-08 23:26:40 +01:00
|
|
|
int imembera;
|
|
|
|
|
extern function new(default);
|
2024-03-02 15:06:54 +01:00
|
|
|
endclass
|
|
|
|
|
|
|
|
|
|
function ClsDefFwd::new(default);
|
|
|
|
|
endfunction
|
|
|
|
|
|
2025-09-13 15:28:43 +02:00
|
|
|
module t;
|
2026-03-08 23:26:40 +01:00
|
|
|
initial begin
|
|
|
|
|
// TODO real test
|
|
|
|
|
$stop;
|
|
|
|
|
end
|
2024-03-02 15:06:54 +01:00
|
|
|
endmodule
|