2020-12-05 22:23:20 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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2020-12-05 22:23:20 +01:00
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// SPDX-License-Identifier: CC0-1.0
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package Pkg;
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2026-03-08 23:26:40 +01:00
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typedef class Fwd;
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virtual class Virt;
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pure virtual function Fwd get_root();
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endclass
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class Ext extends Virt;
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virtual function Fwd get_root();
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return Fwd::m_uvm_get_root();
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endfunction
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endclass
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class Fwd;
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static function Fwd m_uvm_get_root();
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return null;
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endfunction
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endclass
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2020-12-05 22:23:20 +01:00
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endpackage
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