verilator/test_regress/t/t_case_default_bad.out

%Error: t/t_case_default_bad.v:16:7: Multiple default statements in case statement.
   16 |       default: $stop;
      |       ^~~~~~~
        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to
Tests: Verilog format 2026-03-08 23:26:40 +01:00			`%Error: t/t_case_default_bad.v:16:7: Multiple default statements in case statement.`
			`16 \| default: $stop;`
			`\| ^~~~~~~`
Change error messages to more often suggest documentation 2025-04-05 23:10:28 +02:00			`... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.`
Tests: Add additional .out files instead of expects. 2019-06-13 03:49:40 +02:00			`%Error: Exiting due to`