verilator/test_regress/t/t_dfg_break_cycles.py

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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
Optimize complex combinational logic in DFG (#6298) This patch adds DfgLogic, which is a vertex that represents a whole, arbitrarily complex combinational AstAlways or AstAssignW in the DfgGraph. Implementing this requires computing the variables live at entry to the AstAlways (variables read by the block), so there is a new ControlFlowGraph data structure and a classical data-flow analysis based live variable analysis to do that at the variable level (as opposed to bit/element level). The actual CFG construction and live variable analysis is best effort, and might fail for currently unhandled constructs or data types. This can be extended later. V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices. The DfgLogic are then subsequently synthesized into primitive operations by the new V3DfgSynthesize pass, which is a combination of the old V3DfgAstToDfg conversion and new code to handle AstAlways blocks with complex flow control. V3DfgSynthesize by default will synthesize roughly the same constructs as V3DfgAstToDfg used to handle before, plus any logic that is part of a combinational cycle within the DfgGraph. This enables breaking up these cycles, for which there are extensions to V3DfgBreakCycles in this patch as well. V3DfgSynthesize will then delete all non synthesized or non synthesizable DfgLogic vertices and the rest of the Dfg pipeline is identical, with minor changes to adjust for the changed representation. Because with this change we can now eliminate many more UNOPTFLAT, DFG has been disabled in all the tests that specifically target testing the scheduling and reporting of circular combinational logic.
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import os
test.scenarios('vlt_all')
test.sim_time = 2000000
root = ".."
if not os.path.exists(root + "/.git"):
test.skip("Not in a git repository")
# Read expected source lines hit
expectedLines = set()
with open(root + "/src/V3DfgBreakCycles.cpp", 'r', encoding="utf8") as fd:
for lineno, line in enumerate(fd, 1):
line = line.split("//")[0]
if re.match(r'^[^#]*SET_RESULT', line):
expectedLines.add(lineno)
if re.match(r'^[^#]*MASK', line):
expectedLines.add(lineno)
if not expectedLines:
test.error("Failed to read expected source line numbers")
# Generate the equivalence checks and declaration boilerplate
rdFile = test.top_filename
plistFile = test.obj_dir + "/portlist.vh"
pdeclFile = test.obj_dir + "/portdecl.vh"
checkFile = test.obj_dir + "/checks.h"
nExpectedCycles = 0
with open(rdFile, 'r', encoding="utf8") as rdFh, \
open(plistFile, 'w', encoding="utf8") as plistFh, \
open(pdeclFile, 'w', encoding="utf8") as pdeclFh, \
open(checkFile, 'w', encoding="utf8") as checkFh:
for line in rdFh:
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if "// UNOPTFLAT" in line:
nExpectedCycles += 1
line = line.split("//")[0]
m = re.search(r'`signal\((\w+),', line)
if not m:
continue
sig = m.group(1)
plistFh.write(sig + ",\n")
pdeclFh.write("output " + sig + ";\n")
checkFh.write("if (ref." + sig + " != opt." + sig + ") {\n")
checkFh.write(" std::cout << \"Mismatched " + sig + "\" << std::endl;\n")
checkFh.write(" std::cout << \"Ref: 0x\" << std::hex << (ref." + sig +
" + 0) << std::endl;\n")
checkFh.write(" std::cout << \"Opt: 0x\" << std::hex << (opt." + sig +
" + 0) << std::endl;\n")
checkFh.write(" std::exit(1);\n")
checkFh.write("}\n")
# Compile un-optimized
test.compile(verilator_flags2=[
"--stats",
"--build",
"-fno-dfg-break-cycles",
"+incdir+" + test.obj_dir,
"-Mdir", test.obj_dir + "/obj_ref",
"--prefix", "Vref",
"-Wno-UNOPTFLAT"
]) # yapf:disable
# Check we got the expected number of circular logic warnings
test.file_grep(test.obj_dir + "/obj_ref/Vref__stats.txt",
r'Warnings, Suppressed UNOPTFLAT\s+(\d+)', nExpectedCycles)
# Compile optimized - also builds executable
test.compile(verilator_flags2=[
"--stats",
"--build",
"-fno-dfg-post-inline",
"-fno-dfg-scoped",
"--exe",
"+incdir+" + test.obj_dir,
"-Mdir", test.obj_dir + "/obj_opt",
"--prefix", "Vopt",
"-Werror-UNOPTFLAT",
"--dumpi-V3DfgBreakCycles", "9", # To fill code coverage
"--debug", "--debugi", "0", "--dumpi-tree", "0",
"-CFLAGS \"-I .. -I ../obj_ref\"",
"../obj_ref/Vref__ALL.a",
"../../t/" + test.name + ".cpp"
]) # yapf:disable
# Check all source lines hit
coveredLines = set()
def readCovered(fileName):
Optimize complex combinational logic in DFG (#6298) This patch adds DfgLogic, which is a vertex that represents a whole, arbitrarily complex combinational AstAlways or AstAssignW in the DfgGraph. Implementing this requires computing the variables live at entry to the AstAlways (variables read by the block), so there is a new ControlFlowGraph data structure and a classical data-flow analysis based live variable analysis to do that at the variable level (as opposed to bit/element level). The actual CFG construction and live variable analysis is best effort, and might fail for currently unhandled constructs or data types. This can be extended later. V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices. The DfgLogic are then subsequently synthesized into primitive operations by the new V3DfgSynthesize pass, which is a combination of the old V3DfgAstToDfg conversion and new code to handle AstAlways blocks with complex flow control. V3DfgSynthesize by default will synthesize roughly the same constructs as V3DfgAstToDfg used to handle before, plus any logic that is part of a combinational cycle within the DfgGraph. This enables breaking up these cycles, for which there are extensions to V3DfgBreakCycles in this patch as well. V3DfgSynthesize will then delete all non synthesized or non synthesizable DfgLogic vertices and the rest of the Dfg pipeline is identical, with minor changes to adjust for the changed representation. Because with this change we can now eliminate many more UNOPTFLAT, DFG has been disabled in all the tests that specifically target testing the scheduling and reporting of circular combinational logic.
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if not os.path.exists(fileName):
test.error_keep_going("Missing coverage file: " + fileName)
return
with open(fileName, 'r', encoding="utf8") as fd:
for line in fd:
coveredLines.add(int(line.strip()))
readCovered(test.obj_dir + "/obj_opt/Vopt__V3DfgBreakCycles-TraceDriver-line-coverage.txt")
readCovered(test.obj_dir + "/obj_opt/Vopt__V3DfgBreakCycles-IndependentBits-line-coverage.txt")
if coveredLines != expectedLines:
for n in sorted(expectedLines - coveredLines):
test.error_keep_going(f"V3DfgBreakCycles.cpp line {n} not covered")
for n in sorted(coveredLines - expectedLines):
test.error_keep_going(f"V3DfgBreakCycles.cpp line {n} covered but not expected")
test.file_grep_not(test.obj_dir + "/obj_opt/Vopt__stats.txt",
r'DFG.*non-representable.*\s[1-9]\d*$')
# Execute test to check equivalence
test.execute(executable=test.obj_dir + "/obj_opt/Vopt")
test.passes()