39 lines
1.2 KiB
Python
39 lines
1.2 KiB
Python
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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def run(test, *, cmake=False, verilator_flags2=()):
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mode, fmt = test.parse_name(r"t_trace_basic_(cc|sc)_([a-z]+)")
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if mode == "sc" and not test.have_sc:
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test.skip("No SystemC installed")
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# All test use the same SV file
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test.top_filename = "t/t_trace_basic.v"
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# Any variations after the format name must yield the exact same trace
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test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out"
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flags = [
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f"--{mode}",
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f"--trace-{fmt}",
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]
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if mode == "sc":
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flags.append("+define+SYSTEMC")
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flags.extend(verilator_flags2)
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# Run test
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test.compile(verilator_flags2=flags,
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verilator_make_gmake=not cmake,
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verilator_make_cmake=cmake)
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test.execute()
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test.trace_identical(test.trace_filename, test.golden_filename)
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test.passes()
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