2022-10-15 19:24:38 +02:00
|
|
|
$version Generated by VerilatedVcd $end
|
|
|
|
|
$timescale 1ps $end
|
2024-09-23 05:03:51 +02:00
|
|
|
$scope module t $end
|
|
|
|
|
$var wire 32 % CLOCK_CYCLE [31:0] $end
|
|
|
|
|
$var wire 1 # rst $end
|
|
|
|
|
$var wire 1 $ clk $end
|
2022-10-15 19:24:38 +02:00
|
|
|
$upscope $end
|
|
|
|
|
$enddefinitions $end
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#0
|
|
|
|
|
1#
|
|
|
|
|
0$
|
|
|
|
|
b00000000000000000000000000001010 %
|
|
|
|
|
#5
|
|
|
|
|
1$
|
|
|
|
|
#10
|
|
|
|
|
0#
|
|
|
|
|
0$
|
|
|
|
|
#15
|
|
|
|
|
1$
|
|
|
|
|
#20
|
2025-05-02 13:36:42 +02:00
|
|
|
0$
|
