verilator/test_regress/t/t_trace_timing1.out

$version Generated by VerilatedVcd $end
$timescale 1ps $end

 $scope module TOP $end
  $scope module t $end
   $var wire 32 % CLOCK_CYCLE [31:0] $end
   $var wire 1 # rst $end
   $var wire 1 $ clk $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
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b00000000000000000000000000001010 %
#5
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#10
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#15
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#20
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Fix --main --trace missing initial timestep (#3678). 2022-10-15 19:24:38 +02:00			`$version Generated by VerilatedVcd $end`
			`$timescale 1ps $end`

			`$scope module TOP $end`
			`$scope module t $end`
			`$var wire 32 % CLOCK_CYCLE [31:0] $end`
Unify code generation for trace declarations in both trace formats (#4612) This patch adds some abstract enums to pass to the trace decl* APIs, so the VCD/FST specific code can be kept in verilated_{vcd,fst}_.cc, and removed from V3Emit. It also reworks the generation of the trace init functions (those that call 'decl*' for the signals) such that the scope hierarchy is traversed precisely once during initialization, which simplifies the FST writer. This later change also has the side effect of fixing tracing of nested interfaces when traced via an interface reference - see the change in the expected t_interface_ref_trace - which previously were missed. 2023-10-24 17:33:29 +02:00			`$var wire 1 # rst $end`
			`$var wire 1 $ clk $end`
Fix --main --trace missing initial timestep (#3678). 2022-10-15 19:24:38 +02:00			`$upscope $end`
			`$upscope $end`
			`$enddefinitions $end`


			`#0`
			`1#`
			`0$`
			`b00000000000000000000000000001010 %`
			`#5`
			`1$`
			`#10`
			`0#`
			`0$`
			`#15`
			`1$`
			`#20`
			`1#`