2024-11-09 19:14:19 +01:00
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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2025-08-28 09:48:51 +02:00
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test.compile(
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verilator_flags2=["--stats", "--build", "--gate-stmts", "10000", "--expand-limit", "128"])
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2024-11-09 19:14:19 +01:00
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2024-11-10 18:23:11 +01:00
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test.file_grep(test.stats, r'Optimizations, FuncOpt concat trees balanced\s+(\d+)', 1)
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2024-11-10 16:51:59 +01:00
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test.file_grep(test.stats, r'Optimizations, FuncOpt concat splits\s+(\d+)', 62)
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2024-11-09 19:14:19 +01:00
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test.passes()
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