49 lines
976 B
Systemverilog
49 lines
976 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,
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expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module sub (
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input clk,
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input b
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); /*verilator hier_block*/
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reg tmp_clk;
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assign tmp_clk = clk;
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always @(posedge tmp_clk) begin
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$display("[%0t] triggered by clk", $time);
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end
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int count = 0;
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always @(b) begin
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`ifdef TEST_VERBOSE
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$display("[%0t] triggered by b", $time);
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`endif
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++count;
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end
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final `checkd(count, 2);
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endmodule
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic b = 1;
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sub sub (.*);
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc >= 2) begin
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$finish;
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end
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end
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endmodule
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