2024-03-02 15:05:21 +01:00
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%Error: t/t_clocking_bad1.v:16:12: Only one default clocking block allowed per module (IEEE 1800-2023 14.12)
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2023-09-23 14:52:50 +02:00
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: ... note: In instance 't'
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2022-12-23 13:34:49 +01:00
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16 | default clocking @(posedge clk);
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| ^~~~~~~~
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2025-04-05 23:10:28 +02:00
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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2022-12-23 13:34:49 +01:00
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%Error: Exiting due to
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