%Error: t/t_clocking_bad1.v:16:12: Only one default clocking block allowed per module (IEEE 1800-2023 14.12)
                                 : ... note: In instance 't'
   16 |    default clocking @(posedge clk);
      |            ^~~~~~~~
        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to