42 lines
685 B
Systemverilog
42 lines
685 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Alias type check error test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [15:0] out;
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wire [15:0] a;
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alias a = sub_i.btw;
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sub sub_i (
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.clk(clk),
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.out(out)
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);
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endmodule
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module sub (
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input clk,
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output wire [15:0] out
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);
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reg [31:0] counter = 32'h0;
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wire [15:0] btw;
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assign btw = {counter[15:0]};
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assign out = btw;
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always @(posedge clk) begin
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counter += 1;
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end
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endmodule
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