verilator/docs/gen/ex_MULTIDRIVEN_faulty.rst

.. comment: generated by t_lint_multidriven_bad
.. code-block:: sv
   :linenos:
   :emphasize-lines: 2,5

     always @(posedge clk) begin
       out2[7:0] <= d0;  // <--- Warning
     end
     always @(negedge clk) begin
       out2[15:8] <= d0;  // <--- Warning
     end