verilator/test_regress/t/t_interface_missing_bad.v

29 lines
499 B
Systemverilog
Raw Normal View History

// DESCRIPTION: Verilator: Missing interface test
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2015 Todd Strader
// SPDX-License-Identifier: CC0-1.0
// Interface intentionally not defined
//interface foo_intf;
// logic a;
//endinterface
2026-03-08 23:26:40 +01:00
module foo_mod (
foo_intf foo
);
endmodule
module t;
2026-03-08 23:26:40 +01:00
foo_intf the_foo ();
2026-03-08 23:26:40 +01:00
foo_mod foo_mod (.foo(the_foo));
2026-03-08 23:26:40 +01:00
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule