%Error: t/t_inst_misarray2_bad.v:9:17: Illegal input port connection 'i_data', mismatch between port which is not an array, and expression which is an array. (IEEE 1800-2023 7.6)
: ... note: In instance 't'
9 | round round (.i_data(fft_oQ[6:0]));
| ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to
