2024-08-31 01:35:47 +02:00
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// DESCRIPTION: Verilator: SystemVerilog interface test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Iztok Jeras
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2024-08-31 01:35:47 +02:00
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// SPDX-License-Identifier: CC0-1.0
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2026-03-08 23:26:40 +01:00
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interface intf;
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2024-08-31 01:35:47 +02:00
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2026-03-08 23:26:40 +01:00
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function automatic string get_scope;
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string the_scope = $sformatf("%m");
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return the_scope;
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endfunction
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2024-08-31 01:35:47 +02:00
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2026-03-08 23:26:40 +01:00
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initial $display(get_scope());
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2024-08-31 01:35:47 +02:00
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endinterface
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2026-03-08 23:26:40 +01:00
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module t (
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input clk
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);
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2024-08-31 01:35:47 +02:00
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2026-03-08 23:26:40 +01:00
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// finish report
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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2024-08-31 01:35:47 +02:00
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2026-03-08 23:26:40 +01:00
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intf the_intf ();
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2024-08-31 01:35:47 +02:00
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endmodule
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