verilator/test_regress/t/t_initial_assign_sformatf.v

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Systemverilog
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// DESCRIPTION: Verilator: SystemVerilog interface test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2012 Iztok Jeras
// SPDX-License-Identifier: CC0-1.0
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interface intf;
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function automatic string get_scope;
string the_scope = $sformatf("%m");
return the_scope;
endfunction
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initial $display(get_scope());
endinterface
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module t (
input clk
);
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// finish report
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
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intf the_intf ();
endmodule