verilator/test_regress/t/t_bitsel_wire_array_bad.out

%Error: t/t_bitsel_wire_array_bad.v:16:15: Illegal assignment of constant to unpacked array
                                         : ... note: In instance 't'
   16 |   assign b = a[0];   
      |               ^
        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to
Verilog format 2026-03-03 13:21:24 +01:00			`%Error: t/t_bitsel_wire_array_bad.v:16:15: Illegal assignment of constant to unpacked array`
Cleanup some error messages to properly quote 2023-09-23 14:52:50 +02:00			`: ... note: In instance 't'`
Verilog format 2026-03-03 13:21:24 +01:00			`16 \| assign b = a[0];`
			`\| ^`
Change error messages to more often suggest documentation 2025-04-05 23:10:28 +02:00			`... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.`
Tests: Add additional .out files instead of expects. 2019-06-13 03:49:40 +02:00			`%Error: Exiting due to`