51 lines
1.0 KiB
Systemverilog
51 lines
1.0 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module other_sub (
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input wire clk,
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input wire foo,
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output logic [5:0] bar
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);
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always_comb bar[0] = foo;
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`ifndef NO_ASSERT
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assert property (@(posedge clk) (foo == bar[0]));
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`endif
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always_ff @(posedge clk) bar[5:1] <= bar[4:0];
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endmodule
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interface intf
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(input wire clk);
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endinterface
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module sub (
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input logic clk
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);
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for (genvar k = 0; k < 4; k++) begin
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logic [5:0] bar;
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other_sub
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the_other_sub (
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.clk,
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.foo ('1),
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.bar
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);
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end
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endmodule
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module t (/*AUTOARG*/
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clk
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);
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input clk;
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int cyc = 0;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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sub the_sub (.*);
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endmodule
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