verilator/test_regress/t/t_clocking_bad2.out

%Error: t/t_clocking_bad2.v:16:23: Multiple default input skews not allowed
   16 |        default input #2 output #2;
      |                       ^
        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_clocking_bad2.v:16:33: Multiple default output skews not allowed
   16 |        default input #2 output #2;
      |                                 ^
%Error: t/t_clocking_bad2.v:18:8: Multiple clockvars with the same name not allowed
   18 |        output out;
      |        ^~~~~~
%Error: Exiting due to