2008-06-10 03:25:10 +02:00
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# -*- Makefile -*-
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2006-08-26 13:35:28 +02:00
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#*****************************************************************************
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#
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# DESCRIPTION: Verilator: Makefile for verilog source
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#
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2019-11-08 04:33:59 +01:00
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# Code available from: https://verilator.org
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2006-08-26 13:35:28 +02:00
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#
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#*****************************************************************************
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#
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2023-01-01 16:18:39 +01:00
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# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
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2020-03-21 16:24:24 +01:00
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# can redistribute it and/or modify it under the terms of either the GNU
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2009-05-04 23:07:57 +02:00
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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2020-03-21 16:24:24 +01:00
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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2006-08-26 13:35:28 +02:00
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#
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#****************************************************************************/
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#### Start of system configuration section. ####
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2009-11-25 23:20:28 +01:00
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# Unfortunately configure uses relative paths, and this makefile is called
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# from a level lower, so we need to move up if it's relative, not if absolute.
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config_srcdir = @srcdir@
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ifeq ($(config_srcdir),.)
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srcdir = ..
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else # Run an experiment
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2012-02-16 13:17:08 +01:00
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ifeq ($(wildcard $(config_srcdir)/../Makefile_obj.in),)
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2009-11-25 23:20:28 +01:00
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srcdir = $(config_srcdir)
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else
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srcdir = $(config_srcdir)/..
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endif
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endif
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incdir = $(srcdir)/../include
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# Bldsrc may differ from srcdir if configure wan't run from the kit top
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bldsrc = ..
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2006-08-26 13:35:28 +02:00
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2008-06-24 20:50:34 +02:00
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# Programs
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2006-08-26 13:35:28 +02:00
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CC = @CC@
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CXX = @CXX@
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LINK = @CXX@
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2008-06-24 20:50:34 +02:00
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LEX = @LEX@
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LFLAGS = -d
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2020-12-23 21:41:14 +01:00
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PYTHON3 = @PYTHON3@
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2008-06-24 20:50:34 +02:00
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YACC = @YACC@
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2020-04-05 22:10:33 +02:00
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OBJCACHE ?= @OBJCACHE@
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2008-03-18 21:26:37 +01:00
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prefix = @prefix@
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2008-04-29 16:14:20 +02:00
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# Directory in which to install data across multiple architectures
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datarootdir = @datarootdir@
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2008-03-18 21:26:37 +01:00
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# Directory in which to install package specific files
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# Generally ${prefix}/share/verilator
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pkgdatadir = @pkgdatadir@
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2008-06-24 20:50:34 +02:00
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# Compile options
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2011-10-07 12:48:40 +02:00
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CFG_WITH_CCWARN = @CFG_WITH_CCWARN@
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2008-06-24 20:50:34 +02:00
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CFG_WITH_DEFENV = @CFG_WITH_DEFENV@
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2011-08-23 03:02:09 +02:00
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CPPFLAGS += @CPPFLAGS@
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2019-07-06 19:02:36 +02:00
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CFLAGS += @CFLAGS@
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CXXFLAGS += @CXXFLAGS@
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2008-06-24 20:50:34 +02:00
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LDFLAGS += @LDFLAGS@
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2011-10-05 23:07:10 +02:00
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EXEEXT = @EXEEXT@
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2015-02-11 04:38:05 +01:00
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CFG_CXXFLAGS_SRC = @CFG_CXXFLAGS_SRC@
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CFG_CXXFLAGS_PARSER = @CFG_CXXFLAGS_PARSER@
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2017-09-15 05:28:02 +02:00
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# Compiler flags that turn on extra warnings
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CFG_CXXFLAGS_WEXTRA = @CFG_CXXFLAGS_WEXTRA@
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2020-02-01 01:13:55 +01:00
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CFG_LDFLAGS_SRC = @CFG_LDFLAGS_SRC@
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2020-01-23 23:32:19 +01:00
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CFG_LIBS = @CFG_LIBS@
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2008-06-24 20:50:34 +02:00
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2006-08-26 13:35:28 +02:00
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#### End of system configuration section. ####
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2009-11-25 23:20:28 +01:00
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VPATH += . $(bldsrc) $(srcdir)
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2021-06-04 18:04:55 +02:00
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TGT = ../../verilator_bin$(EXEEXT)
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2006-08-26 13:35:28 +02:00
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#################
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2022-01-08 17:18:23 +01:00
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ifeq ($(VL_NOOPT),1)
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CPPFLAGS += -O0
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else ifeq ($(VL_DEBUG),)
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2006-08-26 13:35:28 +02:00
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# Optimize
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2022-09-03 23:10:07 +02:00
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CPPFLAGS += -O3
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2006-08-26 13:35:28 +02:00
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else
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# Debug
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2021-06-12 21:46:08 +02:00
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CPPFLAGS += @CFG_CXXFLAGS_DEBUG@ -DVL_DEBUG -D_GLIBCXX_DEBUG
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LDFLAGS += @CFG_LDFLAGS_DEBUG@
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2006-08-26 13:35:28 +02:00
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endif
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#################
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#LIBS += -ldl
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#CCMALLOC = /usr/local/lib/ccmalloc-gcc.o -lccmalloc -ldl
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2010-02-01 12:37:39 +01:00
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# -lfl not needed as Flex invoked with %nowrap option
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2020-02-01 01:13:55 +01:00
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LIBS = $(CFG_LIBS) -lm
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2006-08-26 13:35:28 +02:00
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2011-08-23 03:02:09 +02:00
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CPPFLAGS += -MMD
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2018-08-25 13:55:48 +02:00
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CPPFLAGS += -I. -I$(bldsrc) -I$(srcdir) -I$(incdir) -I../../include
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2011-08-23 03:02:09 +02:00
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#CPPFLAGS += -DVL_LEAK_CHECKS # If running valgrind or other hunting tool
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CPPFLAGS += -MP # Only works on recent GCC versions
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2011-10-07 12:48:40 +02:00
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ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users
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2017-09-15 05:28:02 +02:00
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CPPFLAGS += -W -Wall $(CFG_CXXFLAGS_WEXTRA) $(CFG_CXXFLAGS_SRC) -Werror
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2006-08-26 13:35:28 +02:00
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#CPPFLAGS += -pedantic-errors
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2016-05-17 03:40:49 +02:00
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else
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CPPFLAGS += $(CFG_CXXFLAGS_SRC)
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2006-08-26 13:35:28 +02:00
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endif
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2020-02-01 01:13:55 +01:00
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LDFLAGS += $(CFG_LDFLAGS_SRC)
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2017-11-02 23:02:11 +01:00
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2011-08-23 03:02:09 +02:00
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CPPFLAGSWALL = $(CPPFLAGS)
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2015-02-11 04:38:05 +01:00
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CPPFLAGSPARSER = $(CPPFLAGS) $(CFG_CXXFLAGS_PARSER)
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2006-08-26 13:35:28 +02:00
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2008-03-18 21:26:37 +01:00
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# Allow RPM builds to specify hardcoded data directories
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# To do this:
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2008-03-28 20:42:14 +01:00
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ifeq ($(CFG_WITH_DEFENV),yes)
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2008-03-18 21:26:37 +01:00
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CPPFLAGS += -DDEFENV_SYSTEMC=\"$(SYSTEMC)\"
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CPPFLAGS += -DDEFENV_SYSTEMC_ARCH=\"$(SYSTEMC_ARCH)\"
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2012-01-20 02:30:41 +01:00
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CPPFLAGS += -DDEFENV_SYSTEMC_INCLUDE=\"$(SYSTEMC_INCLUDE)\"
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CPPFLAGS += -DDEFENV_SYSTEMC_LIBDIR=\"$(SYSTEMC_LIBDIR)\"
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2008-03-18 21:26:37 +01:00
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ifeq ($(VERILATOR_ROOT),) # Use what we're given, or intuit
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CPPFLAGS += -DDEFENV_VERILATOR_ROOT=\"$(pkgdatadir)\"
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else
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CPPFLAGS += -DDEFENV_VERILATOR_ROOT=\"$(VERILATOR_ROOT)\"
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endif
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endif
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2006-08-26 13:35:28 +02:00
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HEADERS = $(wildcard V*.h v*.h)
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ASTGEN = $(srcdir)/astgen
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2008-08-06 18:35:34 +02:00
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BISONPRE = $(srcdir)/bisonpre
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2010-02-27 01:50:44 +01:00
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FLEXFIX = $(srcdir)/flexfix
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2014-11-24 03:06:10 +01:00
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VLCOVGEN = $(srcdir)/vlcovgen
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2006-08-26 13:35:28 +02:00
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######################################################################
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#### Top level
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all: make_info $(TGT)
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make_info:
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2019-07-06 19:02:36 +02:00
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@echo " Compile flags: " $(CXX) ${CFLAGS} ${CXXFLAGS} ${CPPFLAGS}
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2006-08-26 13:35:28 +02:00
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clean mostlyclean distclean maintainer-clean::
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2020-12-23 21:41:14 +01:00
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-rm -f *.o *.d *_gen_*
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2006-08-26 13:35:28 +02:00
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-rm -f *__gen*
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-rm -f obj_* .objcache*
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distclean maintainer-clean:: clean
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maintainer-clean::
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maintainer-copy::
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#### Top executable
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RAW_OBJS = \
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Verilator.o \
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V3Active.o \
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V3ActiveTop.o \
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V3Assert.o \
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V3AssertPre.o \
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V3Ast.o \
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2022-12-11 15:43:42 +01:00
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V3AstNodes.o \
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2006-08-26 13:35:28 +02:00
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V3Begin.o \
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V3Branch.o \
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V3Broken.o \
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2016-10-23 20:27:57 +02:00
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V3CCtors.o \
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2020-02-01 22:45:11 +01:00
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V3CUse.o \
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2006-08-26 13:35:28 +02:00
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V3Case.o \
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V3Cast.o \
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2010-01-07 22:41:19 +01:00
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V3Cdc.o \
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2020-04-05 15:30:23 +02:00
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V3Class.o \
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2006-08-26 13:35:28 +02:00
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V3Clean.o \
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V3Clock.o \
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V3Combine.o \
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2021-07-20 17:40:38 +02:00
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V3Common.o \
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2010-01-21 12:11:30 +01:00
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V3Config.o \
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2006-08-26 13:35:28 +02:00
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V3Const__gen.o \
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V3Coverage.o \
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2008-12-12 21:34:02 +01:00
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V3CoverageJoin.o \
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2006-08-26 13:35:28 +02:00
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V3Dead.o \
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V3Delayed.o \
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V3Depth.o \
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2007-04-19 20:20:16 +02:00
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V3DepthBlock.o \
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2006-08-26 13:35:28 +02:00
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V3Descope.o \
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Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
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V3Dfg.o \
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V3DfgAstToDfg.o \
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2022-10-08 15:34:07 +02:00
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V3DfgDecomposition.o \
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Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
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V3DfgDfgToAst.o \
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V3DfgOptimizer.o \
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V3DfgPasses.o \
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V3DfgPeephole.o \
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2021-05-21 02:41:46 +02:00
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V3DupFinder.o \
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2021-06-24 17:58:30 +02:00
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V3EmitCBase.o \
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2021-06-13 16:05:55 +02:00
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V3EmitCConstPool.o \
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2021-06-24 18:35:12 +02:00
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V3EmitCFunc.o \
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2021-07-07 20:16:40 +02:00
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V3EmitCHeaders.o \
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V3EmitCImp.o \
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2007-11-30 23:38:21 +01:00
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V3EmitCInlines.o \
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2020-04-22 02:45:23 +02:00
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V3EmitCMain.o \
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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V3EmitCMake.o \
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V3EmitCModel.o \
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V3EmitCSyms.o \
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2006-08-26 13:35:28 +02:00
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V3EmitMk.o \
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V3EmitV.o \
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2012-03-20 21:13:10 +01:00
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V3EmitXml.o \
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2006-08-26 13:35:28 +02:00
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V3Error.o \
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V3Expand.o \
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V3File.o \
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2014-11-22 17:48:39 +01:00
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V3FileLine.o \
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2022-01-01 18:24:19 +01:00
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V3Force.o \
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2006-08-26 13:35:28 +02:00
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V3Gate.o \
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2020-01-19 13:23:26 +01:00
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V3Global.o \
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2006-08-26 13:35:28 +02:00
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V3Graph.o \
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V3GraphAcyc.o \
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2022-12-11 15:43:42 +01:00
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V3GraphAlg.o \
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2018-07-16 04:09:27 +02:00
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V3GraphPathChecker.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3GraphTest.o \
|
2021-05-21 15:34:27 +02:00
|
|
|
V3Hash.o \
|
2021-05-21 02:41:46 +02:00
|
|
|
V3Hasher.o \
|
2020-08-15 15:43:53 +02:00
|
|
|
V3HierBlock.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Inline.o \
|
|
|
|
|
V3Inst.o \
|
2018-07-05 03:52:15 +02:00
|
|
|
V3InstrCount.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Life.o \
|
|
|
|
|
V3LifePost.o \
|
|
|
|
|
V3LinkCells.o \
|
|
|
|
|
V3LinkDot.o \
|
2020-05-29 00:08:15 +02:00
|
|
|
V3LinkInc.o \
|
2022-12-11 15:43:42 +01:00
|
|
|
V3LinkJump.o \
|
2006-12-21 15:35:19 +01:00
|
|
|
V3LinkLValue.o \
|
2010-02-14 16:01:21 +01:00
|
|
|
V3LinkLevel.o \
|
2006-12-21 22:53:51 +01:00
|
|
|
V3LinkParse.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3LinkResolve.o \
|
|
|
|
|
V3Localize.o \
|
2020-05-30 22:09:05 +02:00
|
|
|
V3MergeCond.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Name.o \
|
|
|
|
|
V3Number.o \
|
2021-05-03 23:30:18 +02:00
|
|
|
V3OptionParser.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Options.o \
|
|
|
|
|
V3Order.o \
|
2015-02-27 02:40:45 +01:00
|
|
|
V3Os.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Param.o \
|
2022-12-11 15:43:42 +01:00
|
|
|
V3ParseGrammar.o \
|
|
|
|
|
V3ParseImp.o \
|
|
|
|
|
V3ParseLex.o \
|
2018-07-23 02:54:28 +02:00
|
|
|
V3Partition.o \
|
2022-12-11 15:43:42 +01:00
|
|
|
V3PreProc.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3PreShell.o \
|
|
|
|
|
V3Premit.o \
|
2019-10-09 12:47:26 +02:00
|
|
|
V3ProtectLib.o \
|
2020-12-07 23:55:22 +01:00
|
|
|
V3Randomize.o \
|
2018-06-23 23:07:22 +02:00
|
|
|
V3Reloop.o \
|
2022-05-15 17:03:32 +02:00
|
|
|
V3Sched.o \
|
|
|
|
|
V3SchedAcyclic.o \
|
|
|
|
|
V3SchedPartition.o \
|
|
|
|
|
V3SchedReplicate.o \
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
V3SchedTiming.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Scope.o \
|
2018-07-16 04:09:27 +02:00
|
|
|
V3Scoreboard.o \
|
2010-01-19 16:52:11 +01:00
|
|
|
V3Slice.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Split.o \
|
2007-01-18 01:51:26 +01:00
|
|
|
V3SplitAs.o \
|
2020-02-29 01:15:08 +01:00
|
|
|
V3SplitVar.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Stats.o \
|
|
|
|
|
V3StatsReport.o \
|
2012-08-27 03:13:47 +02:00
|
|
|
V3String.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Subst.o \
|
2022-12-11 15:43:42 +01:00
|
|
|
V3TSP.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Table.o \
|
|
|
|
|
V3Task.o \
|
2022-12-11 15:43:42 +01:00
|
|
|
V3Timing.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Trace.o \
|
|
|
|
|
V3TraceDecl.o \
|
2009-01-06 17:03:57 +01:00
|
|
|
V3Tristate.o \
|
2010-12-29 14:06:05 +01:00
|
|
|
V3Undriven.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Unknown.o \
|
|
|
|
|
V3Unroll.o \
|
Add V3VariableOrder pass
A separate V3VariableOrder pass is now used to order module variables
before Emit. All variables are now ordered together, without
consideration for whether they are ports, signals form the design, or
additional internal variables added by Verilator (which used to be
ordered and emitted as separate groups in Emit). For single threaded
models, this is performance neutral. For multi-threaded models, the
MTask affinity based sorting was slightly modified, so variables with no
MTask affinity are emitted last, otherwise the MTask affinity sets are
sorted using the TSP sorter as before, but again, ports, signals, and
internal variables are not differentiated. This yields a 2%+ speedup for
the multithreaded model on OpenTitan.
2021-06-29 18:57:07 +02:00
|
|
|
V3VariableOrder.o \
|
2020-05-26 20:38:14 +02:00
|
|
|
V3Waiver.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
V3Width.o \
|
2009-10-25 21:53:55 +01:00
|
|
|
V3WidthSel.o \
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2014-11-24 03:06:10 +01:00
|
|
|
# verilator_coverage
|
|
|
|
|
VLCOV_OBJS = \
|
|
|
|
|
VlcMain.o \
|
|
|
|
|
|
2022-01-08 17:18:23 +01:00
|
|
|
NON_STANDALONE_HEADERS = \
|
|
|
|
|
V3AstInlines.h \
|
2022-09-15 14:10:39 +02:00
|
|
|
V3AstNodeDType.h \
|
2022-10-12 11:19:21 +02:00
|
|
|
V3AstNodeExpr.h \
|
2022-09-15 14:10:39 +02:00
|
|
|
V3AstNodeOther.h \
|
2022-10-04 12:03:41 +02:00
|
|
|
V3DfgVertices.h \
|
2022-01-08 17:18:23 +01:00
|
|
|
V3WidthCommit.h \
|
|
|
|
|
|
2022-09-15 14:10:39 +02:00
|
|
|
AST_DEFS := \
|
|
|
|
|
V3AstNodeDType.h \
|
2022-10-12 11:19:21 +02:00
|
|
|
V3AstNodeExpr.h \
|
2022-09-15 14:10:39 +02:00
|
|
|
V3AstNodeOther.h \
|
|
|
|
|
|
2022-10-04 12:03:41 +02:00
|
|
|
DFG_DEFS := \
|
|
|
|
|
V3DfgVertices.h
|
|
|
|
|
|
|
|
|
|
#### astgen common flags
|
|
|
|
|
|
|
|
|
|
ASTGENFLAGS = -I $(srcdir)
|
|
|
|
|
ASTGENFLAGS += $(foreach f,$(AST_DEFS),--astdef $f)
|
|
|
|
|
ASTGENFLAGS += $(foreach f,$(DFG_DEFS),--dfgdef $f)
|
|
|
|
|
|
2006-08-26 13:35:28 +02:00
|
|
|
#### Linking
|
|
|
|
|
|
2014-11-24 03:06:10 +01:00
|
|
|
ifeq ($(VL_VLCOV),)
|
2022-10-04 12:03:41 +02:00
|
|
|
PREDEP_H = V3Ast__gen_forward_class_decls.h
|
2022-12-11 15:43:42 +01:00
|
|
|
OBJS += $(RAW_OBJS)
|
2006-08-26 13:35:28 +02:00
|
|
|
else
|
2014-11-24 03:06:10 +01:00
|
|
|
PREDEP_H =
|
|
|
|
|
OBJS += $(VLCOV_OBJS)
|
2006-08-26 13:35:28 +02:00
|
|
|
endif
|
|
|
|
|
|
2014-11-24 03:06:10 +01:00
|
|
|
$(TGT): $(PREDEP_H) $(OBJS)
|
2006-08-26 13:35:28 +02:00
|
|
|
@echo " Linking $@..."
|
|
|
|
|
${LINK} ${LDFLAGS} -o $@ $(OBJS) $(CCMALLOC) ${LIBS}
|
|
|
|
|
|
|
|
|
|
V3Number_test: V3Number_test.o
|
|
|
|
|
${LINK} ${LDFLAGS} -o $@ $^ ${LIBS}
|
|
|
|
|
|
|
|
|
|
#### Modules
|
|
|
|
|
|
2022-10-04 12:03:41 +02:00
|
|
|
%__gen.cpp: %.cpp $(ASTGEN) $(AST_DEFS) $(DFG_DEFS)
|
|
|
|
|
$(PYTHON3) $(ASTGEN) $(ASTGENFLAGS) $*.cpp
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2022-12-16 01:53:51 +01:00
|
|
|
.SECONDARY:
|
2022-12-16 01:26:54 +01:00
|
|
|
|
2006-08-26 13:35:28 +02:00
|
|
|
%.o: %.cpp
|
2020-05-28 23:39:20 +02:00
|
|
|
$(OBJCACHE) ${CXX} ${CXXFLAGS} ${CPPFLAGSWALL} -c $< -o $@
|
2006-08-26 13:35:28 +02:00
|
|
|
%.o: %.c
|
2020-05-28 23:39:20 +02:00
|
|
|
$(OBJCACHE) ${CC} ${CFLAGS} ${CPPFLAGSWALL} -c $< -o $@
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2009-10-31 15:08:38 +01:00
|
|
|
V3ParseLex.o: V3ParseLex.cpp V3Lexer.yy.cpp V3ParseBison.c
|
2020-05-28 23:39:20 +02:00
|
|
|
$(OBJCACHE) ${CXX} ${CXXFLAGS} ${CPPFLAGSPARSER} -c $< -o $@
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2009-10-31 15:08:38 +01:00
|
|
|
V3ParseGrammar.o: V3ParseGrammar.cpp V3ParseBison.c
|
2020-05-28 23:39:20 +02:00
|
|
|
$(OBJCACHE) ${CXX} ${CXXFLAGS} ${CPPFLAGSPARSER} -c $< -o $@
|
2009-10-31 15:08:38 +01:00
|
|
|
|
|
|
|
|
V3ParseImp.o: V3ParseImp.cpp V3ParseBison.c
|
2020-05-28 23:39:20 +02:00
|
|
|
$(OBJCACHE) ${CXX} ${CXXFLAGS} ${CPPFLAGSPARSER} -c $< -o $@
|
2006-08-26 13:35:28 +02:00
|
|
|
|
|
|
|
|
V3PreProc.o: V3PreProc.cpp V3PreLex.yy.cpp
|
2020-05-28 23:39:20 +02:00
|
|
|
$(OBJCACHE) ${CXX} ${CXXFLAGS} ${CPPFLAGSPARSER} -c $< -o $@
|
2006-08-26 13:35:28 +02:00
|
|
|
|
|
|
|
|
#### Generated files
|
|
|
|
|
|
|
|
|
|
# Target rule called before parallel build to make generated files
|
2022-10-04 12:03:41 +02:00
|
|
|
serial:: V3Ast__gen_forward_class_decls.h V3ParseBison.c
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2014-11-24 03:06:10 +01:00
|
|
|
serial_vlcov:: vlcovgen.d
|
|
|
|
|
|
2016-11-19 03:13:56 +01:00
|
|
|
vlcovgen.d: $(VLCOVGEN) $(srcdir)/../include/verilated_cov_key.h
|
2021-01-28 21:01:33 +01:00
|
|
|
$(PYTHON3) $(VLCOVGEN) --srcdir $(srcdir)
|
2014-11-24 03:06:10 +01:00
|
|
|
touch $@
|
|
|
|
|
|
2022-10-04 12:03:41 +02:00
|
|
|
V3Ast__gen_forward_class_decls.h: $(ASTGEN) $(AST_DEFS) $(DFG_DEFS)
|
|
|
|
|
$(PYTHON3) $(ASTGEN) $(ASTGENFLAGS) --classes
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2009-05-05 03:54:44 +02:00
|
|
|
V3ParseBison.h: V3ParseBison.c
|
2008-05-06 17:45:41 +02:00
|
|
|
|
|
|
|
|
# Have only one output file in this rule to prevent parallel make issues
|
2009-05-08 00:28:05 +02:00
|
|
|
V3ParseBison.c: verilog.y $(BISONPRE)
|
2006-08-26 13:35:28 +02:00
|
|
|
@echo "If you get errors from verilog.y below, try upgrading bison to version 1.875 or newer."
|
2021-01-11 04:53:59 +01:00
|
|
|
$(PYTHON3) $(BISONPRE) --yacc ${YACC} -d -v -o V3ParseBison.c $<
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2009-05-05 03:54:44 +02:00
|
|
|
V3Lexer_pregen.yy.cpp: verilog.l V3ParseBison.h $(HEADERS)
|
2009-04-09 03:47:48 +02:00
|
|
|
${LEX} --version
|
2006-08-26 13:35:28 +02:00
|
|
|
${LEX} ${LFLAGS} -o$@ $<
|
|
|
|
|
|
2010-02-27 01:50:44 +01:00
|
|
|
V3Lexer.yy.cpp: V3Lexer_pregen.yy.cpp $(FLEXFIX)
|
2020-12-23 21:41:14 +01:00
|
|
|
$(PYTHON3) $(FLEXFIX) V3Lexer <$< >$@
|
2006-08-26 13:35:28 +02:00
|
|
|
|
|
|
|
|
V3PreLex_pregen.yy.cpp: V3PreLex.l $(HEADERS)
|
2009-04-09 03:47:48 +02:00
|
|
|
${LEX} --version
|
2006-08-26 13:35:28 +02:00
|
|
|
${LEX} ${LFLAGS} -o$@ $<
|
|
|
|
|
|
2010-02-27 01:50:44 +01:00
|
|
|
V3PreLex.yy.cpp: V3PreLex_pregen.yy.cpp $(FLEXFIX)
|
2021-02-26 03:19:37 +01:00
|
|
|
$(PYTHON3) $(FLEXFIX) V3PreLex <$< >$@
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2022-01-08 17:18:23 +01:00
|
|
|
# For t_dist_header_cc
|
|
|
|
|
HEADER_CC_H := $(filter-out $(NON_STANDALONE_HEADERS), $(notdir $(wildcard $(srcdir)/*.h)))
|
|
|
|
|
|
|
|
|
|
.PHONY: header_cc
|
|
|
|
|
header_cc: $(addsuffix __header_cc.o, $(basename $(HEADER_CC_H)))
|
|
|
|
|
|
|
|
|
|
%__header_cc.cpp: %.h
|
2023-01-21 20:40:22 +01:00
|
|
|
$(PYTHON3) $(srcdir)/../bin/verilator_includer $^ > $@
|
2022-01-08 17:18:23 +01:00
|
|
|
|
2015-11-28 23:33:01 +01:00
|
|
|
.SUFFIXES:
|
|
|
|
|
|
2006-08-26 13:35:28 +02:00
|
|
|
######################################################################
|
|
|
|
|
######################################################################
|
|
|
|
|
|
|
|
|
|
DEPS := $(wildcard *.d)
|
|
|
|
|
ifneq ($(DEPS),)
|
|
|
|
|
include $(DEPS)
|
|
|
|
|
endif
|