Add MergeCond pass to combine assignments with ?: on rhs (#2376)
This provides minor simulation performance benefit, but can provide large C++ compilation time improvement, notably with Clang (4x). This patch implements #2366 .
This commit is contained in:
Geza Lore
GitHub
parent
18870f8b62
commit
fe306a36b8
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@ -217,6 +217,7 @@ RAW_OBJS = \
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V3LinkParse.o \
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V3LinkResolve.o \
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V3Localize.o \
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V3MergeCond.o \
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V3Name.o \
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V3Number.o \
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V3Options.o \
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@ -0,0 +1,340 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Merge branches/ternary ?:
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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// Copyright 2003-2020 by Wilson Snyder. This program is free software; you
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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// V3BranchMerge's Transformations:
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//
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// Look for sequences of assignments with ternary conditional on the right
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// hand side with the same condition:
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// lhs0 = cond ? then0 : else0;
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// lhs1 = cond ? then1 : else1;
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// lhs2 = cond ? then2 : else2;
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//
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// This seems to be a common pattern and can make the C compiler take a
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// long time when compiling it with optimization. For us it's easy and fast
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// to convert this to 'if' statements because we know the pattern is common:
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// if (cond) {
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// lhs0 = then0;
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// lhs1 = then1;
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// lhs2 = then2;
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// } else {
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// lhs0 = else0;
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// lhs1 = else1;
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// lhs2 = else2;
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// }
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//
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// For 1-bit signals, we consider strength reduced forms to be conditionals,
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// but only if we already encountered a true conditional we can merge with.
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// If we did, then act as if:
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// 'lhs = cond & value' is actually 'lhs = cond ? value : 1'd0'
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// 'lhs = cond' is actually 'lhs = cond ? 1'd1 : 1'd0'.
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//
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//*************************************************************************
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#include "config_build.h"
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#include "verilatedos.h"
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#include "V3Global.h"
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#include "V3MergeCond.h"
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#include "V3Stats.h"
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#include "V3Ast.h"
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//######################################################################
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class CheckMergeableVisitor : public AstNVisitor {
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private:
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// STATE
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bool m_mergeable; // State tracking whether tree being processed is a mergeable condition
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// METHODS
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VL_DEBUG_FUNC; // Declare debug()
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void clearMergeable(const AstNode* nodep, const char* reason) {
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UASSERT_OBJ(m_mergeable, nodep, "Should have short-circuited traversal");
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m_mergeable = false;
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UINFO(9, "Clearing mergeable on " << nodep << " due to " << reason << endl);
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}
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// VISITORS
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virtual void visit(AstNode* nodep) VL_OVERRIDE {
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if (!m_mergeable) return;
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// Clear if node is impure
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if (!nodep->isPure()) {
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clearMergeable(nodep, "impure");
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return;
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}
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iterateChildrenConst(nodep);
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}
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virtual void visit(AstVarRef* nodep) VL_OVERRIDE {
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if (!m_mergeable) return;
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// Clear if it's an LValue referencing a marked variable
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if (nodep->lvalue() && nodep->varp()->user1()) {
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clearMergeable(nodep, "might modify condition");
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}
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}
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public:
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CheckMergeableVisitor()
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: m_mergeable(false) {}
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// Return false if this node should not be merged at all because:
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// - It contains an impure expression
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// - It contains an LValue referencing the condition
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bool operator()(const AstNodeAssign* node) {
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m_mergeable = true;
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iterateChildrenConst(const_cast<AstNodeAssign*>(node));
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return m_mergeable;
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}
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};
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class MarkVarsVisitor : public AstNVisitor {
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private:
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// METHODS
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VL_DEBUG_FUNC; // Declare debug()
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// VISITORS
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virtual void visit(AstVarRef* nodep) VL_OVERRIDE { nodep->varp()->user1(1); }
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virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildrenConst(nodep); }
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public:
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// Set user1 on all referenced AstVar
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void operator()(AstNode* node) {
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AstNode::user1ClearTree();
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iterate(node);
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}
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};
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class MergeCondVisitor : public AstNVisitor {
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private:
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// NODE STATE
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// AstVar::user1 -> Flag set for variables referenced by m_mgCondp
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AstUser1InUse m_user1InUse;
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// STATE
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VDouble0 m_statMerges; // Statistic tracking
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VDouble0 m_statMergedItems; // Statistic tracking
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VDouble0 m_statLongestList; // Statistic tracking
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AstNode* m_mgFirstp; // First node in merged sequence
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AstNode* m_mgCondp; // The condition of the first node
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AstNode* m_mgLastp; // Last node in merged sequence
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const AstNode* m_mgNextp; // Next node in list being examined
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uint32_t m_listLenght; // Length of current list
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CheckMergeableVisitor m_checkMergeable; // Sub visitor for encapsulation & speed
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MarkVarsVisitor m_markVars; // Sub visitor for encapsulation & speed
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// METHODS
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VL_DEBUG_FUNC; // Declare debug()
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// This function extracts the Cond node from the RHS, if there is one and
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// it is in a supported position, which are:
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// - RHS is the Cond
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// - RHS is And(Const, Cond). This And is inserted often by V3Clean.
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AstNodeCond* extractCond(AstNode* rhsp) {
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if (AstNodeCond* const condp = VN_CAST(rhsp, NodeCond)) {
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return condp;
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} else if (AstAnd* const andp = VN_CAST(rhsp, And)) {
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if (AstNodeCond* const condp = VN_CAST(andp->rhsp(), NodeCond)) {
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if (VN_IS(andp->lhsp(), Const)) { return condp; }
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}
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}
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return NULL;
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}
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// Apply (_ & 1'b1), iff node is wider than 1 bit. This is necessary
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// because this pass is after V3Clean, and sometimes we have an AstAnd with
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// a 1-bit condition on one side, but a more than 1-bit value on the other
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// side, so we need to keep only the LSB.
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AstNode* maskLsb(AstNode* nodep) {
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if (nodep->width1()) {
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return nodep;
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} else {
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AstNode* const maskp = new AstConst(nodep->fileline(), AstConst::LogicTrue());
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return new AstAnd(nodep->fileline(), nodep, maskp);
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}
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}
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// Fold the RHS expression assuming the given condition state. Unlink bits
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// from the RHS which is only used once, and can be reused. What remains
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// of the RHS is expected to be deleted by the caller.
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AstNode* foldAndUnlink(AstNode* rhsp, bool condTrue) {
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if (rhsp->sameTree(m_mgCondp)) {
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return condTrue ? new AstConst(rhsp->fileline(), AstConst::LogicTrue())
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: new AstConst(rhsp->fileline(), AstConst::LogicFalse());
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} else if (AstNodeCond* const condp = extractCond(rhsp)) {
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AstNode* const resp
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= condTrue ? condp->expr1p()->unlinkFrBack() : condp->expr2p()->unlinkFrBack();
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if (condp == rhsp) { return resp; }
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if (AstAnd* const andp = VN_CAST(rhsp, And)) {
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UASSERT_OBJ(andp->rhsp() == condp, rhsp, "Should not try to fold this");
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return new AstAnd(andp->fileline(), andp->lhsp()->cloneTree(false), resp);
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}
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} else if (AstAnd* const andp = VN_CAST(rhsp, And)) {
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if (andp->lhsp()->sameTree(m_mgCondp)) {
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return condTrue ? maskLsb(andp->rhsp()->unlinkFrBack())
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: new AstConst(rhsp->fileline(), AstConst::LogicFalse());
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} else {
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UASSERT_OBJ(andp->rhsp()->sameTree(m_mgCondp), rhsp,
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"AstAnd doesn't hold condition expression");
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return condTrue ? maskLsb(andp->lhsp()->unlinkFrBack())
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: new AstConst(rhsp->fileline(), AstConst::LogicFalse());
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}
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}
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rhsp->v3fatal("Don't know how to fold expression");
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}
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void mergeEnd() {
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UASSERT(m_mgFirstp, "mergeEnd without list");
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// Merge if list is longer than one node
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if (m_mgFirstp != m_mgLastp) {
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UINFO(6, "MergeCond - First: " << m_mgFirstp << " Last: " << m_mgLastp << endl);
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++m_statMerges;
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if (m_listLenght > m_statLongestList) m_statLongestList = m_listLenght;
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// Create equivalent 'if' statement and insert it before the first node
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AstIf* const ifp
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= new AstIf(m_mgCondp->fileline(), m_mgCondp->unlinkFrBack(), NULL, NULL);
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m_mgFirstp->replaceWith(ifp);
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ifp->addNextHere(m_mgFirstp);
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// Unzip the list and insert under branches
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AstNode* nextp = m_mgFirstp;
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do {
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// Grab next pointer and unlink
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AstNode* const currp = nextp;
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nextp = currp != m_mgLastp ? currp->nextp() : NULL;
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currp->unlinkFrBack();
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// Skip over comments
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if (VN_IS(currp, Comment)) {
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VL_DO_DANGLING(currp->deleteTree(), currp);
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continue;
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}
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// Count
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++m_statMergedItems;
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// Unlink RHS and clone to get the 2 assignments (reusing currp)
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AstNodeAssign* const thenp = VN_CAST(currp, NodeAssign);
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AstNode* const rhsp = thenp->rhsp()->unlinkFrBack();
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AstNodeAssign* const elsep = thenp->cloneTree(false);
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// Construct the new RHSs and add to branches
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thenp->rhsp(foldAndUnlink(rhsp, true));
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elsep->rhsp(foldAndUnlink(rhsp, false));
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ifp->addIfsp(thenp);
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ifp->addElsesp(elsep);
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// Cleanup
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VL_DO_DANGLING(rhsp->deleteTree(), rhsp);
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} while (nextp);
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}
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// Reset state
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m_mgFirstp = NULL;
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m_mgCondp = NULL;
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m_mgLastp = NULL;
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m_mgNextp = NULL;
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}
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void addToList(AstNode* nodep, AstNode* condp) {
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// Set up head of new list if node is first in list
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if (!m_mgFirstp) {
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UASSERT_OBJ(condp, nodep, "Cannot start new list without condition");
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m_mgFirstp = nodep;
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m_mgCondp = condp;
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m_listLenght = 0;
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m_markVars(condp);
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}
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// Add node
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++m_listLenght;
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// Track end of list
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m_mgLastp = nodep;
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// Set up expected next node in list. Skip over any comments, (inserted
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// by V3Order before always blocks)
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m_mgNextp = nodep->nextp();
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while (m_mgNextp && VN_IS(m_mgNextp, Comment)) { m_mgNextp = m_mgNextp->nextp(); }
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// If last under parent, done with current list
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if (!m_mgNextp) mergeEnd();
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}
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// VISITORS
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virtual void visit(AstNodeAssign* nodep) VL_OVERRIDE {
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AstNode* const rhsp = nodep->rhsp();
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if (AstNodeCond* const condp = extractCond(rhsp)) {
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if (!m_checkMergeable(nodep)) {
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// Node not mergeable.
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// Finish current list if any, do not start a new one.
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if (m_mgFirstp) mergeEnd();
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return;
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}
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if (m_mgFirstp && (m_mgNextp != nodep || !condp->condp()->sameTree(m_mgCondp))) {
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// Node in different list, or has different condition.
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// Finish current list, addToList will start a new one.
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mergeEnd();
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}
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// Add current node
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addToList(nodep, condp->condp());
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} else if (m_mgFirstp) {
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// RHS is not a conditional, but we already started a list.
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// If it's a 1-bit signal, and a mergeable assignment, try reduced forms
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if (rhsp->widthMin() == 1 && m_checkMergeable(nodep)) {
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// Is it a 'lhs = cond & value' or 'lhs = value & cond'?
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if (AstAnd* const andp = VN_CAST(rhsp, And)) {
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if (andp->lhsp()->sameTree(m_mgCondp) || andp->rhsp()->sameTree(m_mgCondp)) {
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addToList(nodep, NULL);
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return;
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}
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}
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// Is it simply 'lhs = cond'?
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if (rhsp->sameTree(m_mgCondp)) {
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addToList(nodep, NULL);
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return;
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}
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}
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// Not added to list, so we are done with the current list
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mergeEnd();
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}
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}
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virtual void visit(AstComment*) VL_OVERRIDE {} // Skip over comments
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// For speed, only iterate what is necessary.
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virtual void visit(AstNetlist* nodep) VL_OVERRIDE { iterateAndNextNull(nodep->modulesp()); }
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virtual void visit(AstNodeModule* nodep) VL_OVERRIDE { iterateAndNextNull(nodep->stmtsp()); }
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virtual void visit(AstCFunc* nodep) VL_OVERRIDE {
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iterateChildren(nodep);
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// Close list, if there is one at the end of the function
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if (m_mgFirstp) mergeEnd();
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}
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virtual void visit(AstNodeStmt* nodep) VL_OVERRIDE { iterateChildren(nodep); }
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virtual void visit(AstNode* nodep) VL_OVERRIDE {}
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public:
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// CONSTRUCTORS
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explicit MergeCondVisitor(AstNetlist* nodep) {
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m_mgFirstp = NULL;
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m_mgCondp = NULL;
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m_mgLastp = NULL;
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m_mgNextp = NULL;
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m_listLenght = 0;
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iterate(nodep);
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}
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virtual ~MergeCondVisitor() {
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V3Stats::addStat("Optimizations, MergeCond merges", m_statMerges);
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V3Stats::addStat("Optimizations, MergeCond merged items", m_statMergedItems);
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V3Stats::addStat("Optimizations, MergeCond longest merge", m_statLongestList);
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}
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};
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//######################################################################
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// MergeConditionals class functions
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void V3MergeCond::mergeAll(AstNetlist* nodep) {
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UINFO(2, __FUNCTION__ << ": " << endl);
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{ MergeCondVisitor visitor(nodep); }
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V3Global::dumpCheckGlobalTree("merge_cond", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 6);
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}
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@ -0,0 +1,33 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Recreate loops to help pack caches
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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// Copyright 2003-2020 by Wilson Snyder. This program is free software; you
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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#ifndef _V3MERGECOND_H_
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#define _V3MERGECOND_H_ 1
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#include "config_build.h"
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#include "verilatedos.h"
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#include "V3Error.h"
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#include "V3Ast.h"
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//============================================================================
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class V3MergeCond {
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public:
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static void mergeAll(AstNetlist* nodep);
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};
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#endif // Guard
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@ -917,12 +917,12 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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case 'b': m_oCombine = flag; break;
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case 'c': m_oConst = flag; break;
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case 'd': m_oDedupe = flag; break;
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case 'm': m_oAssemble = flag; break;
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case 'e': m_oCase = flag; break;
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case 'g': m_oGate = flag; break;
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case 'i': m_oInline = flag; break;
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case 'k': m_oSubstConst = flag; break;
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case 'l': m_oLife = flag; break;
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case 'm': m_oAssemble = flag; break;
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case 'p':
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m_public = !flag;
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break; // With -Op so flag=0, we want public on so few optimizations done
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@ -931,6 +931,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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case 't': m_oLifePost = flag; break;
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case 'u': m_oSubst = flag; break;
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case 'v': m_oReloop = flag; break;
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case 'w': m_oMergeCond = flag; break;
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case 'x': m_oExpand = flag; break;
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case 'y': m_oAcycSimp = flag; break;
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case 'z': m_oLocalize = flag; break;
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@ -1706,23 +1707,24 @@ void V3Options::optimize(int level) {
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// Set all optimizations to on/off
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bool flag = level > 0;
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m_oAcycSimp = flag;
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m_oAssemble = flag;
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m_oCase = flag;
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m_oCombine = flag;
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m_oConst = flag;
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m_oDedupe = flag;
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m_oExpand = flag;
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m_oGate = flag;
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m_oInline = flag;
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m_oLife = flag;
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m_oLifePost = flag;
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m_oLocalize = flag;
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m_oMergeCond = flag;
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m_oReloop = flag;
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m_oReorder = flag;
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m_oSplit = flag;
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m_oSubst = flag;
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m_oSubstConst = flag;
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m_oTable = flag;
|
||||
m_oDedupe = flag;
|
||||
m_oAssemble = flag;
|
||||
// And set specific optimization levels
|
||||
if (level >= 3) {
|
||||
m_inlineMult = -1; // Maximum inlining
|
||||
|
|
|
|||
|
|
@ -329,17 +329,18 @@ private:
|
|||
// MEMBERS (optimizations)
|
||||
// // main switch: -Op: --public
|
||||
bool m_oAcycSimp; // main switch: -Oy: acyclic pre-optimizations
|
||||
bool m_oAssemble; // main switch: -Om: assign assemble
|
||||
bool m_oCase; // main switch: -Oe: case tree conversion
|
||||
bool m_oCombine; // main switch: -Ob: common icode packing
|
||||
bool m_oConst; // main switch: -Oc: constant folding
|
||||
bool m_oDedupe; // main switch: -Od: logic deduplication
|
||||
bool m_oAssemble; // main switch: -Om: assign assemble
|
||||
bool m_oExpand; // main switch: -Ox: expansion of C macros
|
||||
bool m_oGate; // main switch: -Og: gate wire elimination
|
||||
bool m_oInline; // main switch: -Oi: module inlining
|
||||
bool m_oLife; // main switch: -Ol: variable lifetime
|
||||
bool m_oLifePost; // main switch: -Ot: delayed assignment elimination
|
||||
bool m_oLocalize; // main switch: -Oz: convert temps to local variables
|
||||
bool m_oInline; // main switch: -Oi: module inlining
|
||||
bool m_oMergeCond; // main switch: -Ob: merge conditionals
|
||||
bool m_oReloop; // main switch: -Ov: reform loops
|
||||
bool m_oReorder; // main switch: -Or: reorder assignments in blocks
|
||||
bool m_oSplit; // main switch: -Os: always assignment splitting
|
||||
|
|
@ -548,18 +549,18 @@ public:
|
|||
|
||||
// ACCESSORS (optimization options)
|
||||
bool oAcycSimp() const { return m_oAcycSimp; }
|
||||
bool oAssemble() const { return m_oAssemble; }
|
||||
bool oCase() const { return m_oCase; }
|
||||
bool oCombine() const { return m_oCombine; }
|
||||
bool oConst() const { return m_oConst; }
|
||||
bool oDedupe() const { return m_oDedupe; }
|
||||
bool oAssemble() const { return m_oAssemble; }
|
||||
bool oExpand() const { return m_oExpand; }
|
||||
bool oGate() const { return m_oGate; }
|
||||
bool oDup() const { return oLife(); }
|
||||
bool oInline() const { return m_oInline; }
|
||||
bool oLife() const { return m_oLife; }
|
||||
bool oLifePost() const { return m_oLifePost; }
|
||||
bool oLocalize() const { return m_oLocalize; }
|
||||
bool oInline() const { return m_oInline; }
|
||||
bool oMergeCond() const { return m_oMergeCond; }
|
||||
bool oReloop() const { return m_oReloop; }
|
||||
bool oReorder() const { return m_oReorder; }
|
||||
bool oSplit() const { return m_oSplit; }
|
||||
|
|
|
|||
|
|
@ -65,6 +65,7 @@
|
|||
#include "V3LinkParse.h"
|
||||
#include "V3LinkResolve.h"
|
||||
#include "V3Localize.h"
|
||||
#include "V3MergeCond.h"
|
||||
#include "V3Name.h"
|
||||
#include "V3Order.h"
|
||||
#include "V3Os.h"
|
||||
|
|
@ -423,13 +424,18 @@ static void process() {
|
|||
V3Dead::deadifyAll(v3Global.rootp());
|
||||
}
|
||||
|
||||
if (!v3Global.opt.lintOnly() && !v3Global.opt.xmlOnly() && v3Global.opt.oReloop()) {
|
||||
// Reform loops to reduce code size
|
||||
// Must be after all Sel/array index based optimizations
|
||||
V3Reloop::reloopAll(v3Global.rootp());
|
||||
}
|
||||
|
||||
if (!v3Global.opt.lintOnly() && !v3Global.opt.xmlOnly()) {
|
||||
if (v3Global.opt.oMergeCond()) {
|
||||
// Merge conditionals
|
||||
V3MergeCond::mergeAll(v3Global.rootp());
|
||||
}
|
||||
|
||||
if (v3Global.opt.oReloop()) {
|
||||
// Reform loops to reduce code size
|
||||
// Must be after all Sel/array index based optimizations
|
||||
V3Reloop::reloopAll(v3Global.rootp());
|
||||
}
|
||||
|
||||
// Fix very deep expressions
|
||||
// Mark evaluation functions as member functions, if needed.
|
||||
V3Depth::depthAll(v3Global.rootp());
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(vlt_all => 1);
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ["-unroll-count 64", "--stats"],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
if ($Self->{vlt}) {
|
||||
# Note, with vltmt this might be split differently, so only checking vlt
|
||||
file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i,
|
||||
10);
|
||||
file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/i,
|
||||
640);
|
||||
file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/i,
|
||||
64);
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2020 by Geza Lore.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); $stop; end while(0)
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc= 64'h5aef0c8d_d70a4497;
|
||||
reg [63:0] prev_crc;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
|
||||
prev_crc <= crc;
|
||||
if (cyc==99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
wire cond2 = &crc[1:0];
|
||||
wire cond3 = &crc[2:0];
|
||||
|
||||
reg shuf_q [63:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg bits [63:0];
|
||||
reg shuf_a [63:0];
|
||||
reg shuf_b [63:0];
|
||||
reg shuf_c [63:0];
|
||||
reg shuf_d [63:0];
|
||||
reg shuf_e [63:0];
|
||||
|
||||
// Unpack these to test core algorithm
|
||||
for (int i = 0; i < 64; i = i + 1) begin
|
||||
bits[i] = crc[i];
|
||||
end
|
||||
|
||||
for (int i = 0; i < 64; i = i + 1) begin
|
||||
shuf_a[i] = cyc[0] ? bits[i] : bits[63-i];
|
||||
end
|
||||
|
||||
if (cyc[1]) begin
|
||||
for (int i = 0; i < 64; i = i + 1) begin
|
||||
shuf_b[i] = cyc[0] ? bits[i] : bits[63-i];
|
||||
end
|
||||
end else begin
|
||||
for (int i = 0; i < 64; i = i + 1) begin
|
||||
shuf_b[i] = cyc[0] ? bits[63-i] : bits[i];
|
||||
end
|
||||
end
|
||||
|
||||
// Also test merge under clean/bit extract
|
||||
for (int i = 0; i < 64; i = i + 1) begin
|
||||
shuf_c[i] = cyc[0] ? crc[i] : crc[63-i];
|
||||
end
|
||||
|
||||
// Merge with 'cond & value', 'value & cond', or 'cond'
|
||||
shuf_d[0] = cond2 ? bits[0] : bits[63];
|
||||
for (int i = 1; i < 32; i = i + 2) begin
|
||||
shuf_d[i] = cond2 & bits[i];
|
||||
end
|
||||
for (int i = 2; i < 32; i = i + 2) begin
|
||||
shuf_d[i] = bits[i] & cond2;
|
||||
end
|
||||
for (int i = 32; i < 64; i = i + 1) begin
|
||||
shuf_d[i] = cond2;
|
||||
end
|
||||
|
||||
// Merge with an '&' also used for masking of LSB.
|
||||
shuf_e[0] = cond3 ? bits[0] : bits[63];
|
||||
for (int i = 1; i < 64; i = i + 1) begin
|
||||
shuf_e[i] = cond3 & crc[0];
|
||||
end
|
||||
|
||||
// Also delayed..
|
||||
for (int i = 0; i < 64; i = i + 1) begin
|
||||
shuf_q[i] <= cyc[0] ? crc[i] : crc[63-i];
|
||||
end
|
||||
|
||||
// Check results
|
||||
|
||||
if (cyc[0]) begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[i]);
|
||||
end else begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[63-i]);
|
||||
end
|
||||
|
||||
if (cyc[0] ~^ cyc[1]) begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[i]);
|
||||
end else begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[63-i]);
|
||||
end
|
||||
|
||||
if (cyc[0]) begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[i]);
|
||||
end else begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[63-i]);
|
||||
end
|
||||
|
||||
if (cond2) begin
|
||||
`check(shuf_d[0], crc[0]);
|
||||
for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], crc[i]);
|
||||
for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd1);
|
||||
end else begin
|
||||
`check(shuf_d[0], crc[63]);
|
||||
for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], 1'b0);
|
||||
for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd0);
|
||||
end
|
||||
|
||||
if (cond3) begin
|
||||
`check(shuf_e[0], crc[0]);
|
||||
for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], crc[0]);
|
||||
end else begin
|
||||
`check(shuf_e[0], crc[63]);
|
||||
for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], 1'b0);
|
||||
end
|
||||
|
||||
if (cyc > 0) begin
|
||||
if (~cyc[0]) begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[i]);
|
||||
end else begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[63-i]);
|
||||
end
|
||||
|
||||
if (((cyc - 1) >> 1) % 2 == 1) begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[i]);
|
||||
end else begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[63-i]);
|
||||
end
|
||||
end
|
||||
|
||||
if (cyc[2]) begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[i]);
|
||||
end else begin
|
||||
for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[63-i]);
|
||||
end
|
||||
end
|
||||
|
||||
// Generated always
|
||||
reg shuf_g [63:0];
|
||||
generate for (genvar i = 0 ; i < 64; i = i + 1)
|
||||
always @(posedge clk) begin
|
||||
shuf_g[i] <= cyc[1] ? crc[i] : crc[63-i];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Generated assign
|
||||
wire shuf_w [63:0];
|
||||
generate for (genvar i = 0 ; i < 64; i = i + 1)
|
||||
assign shuf_w[i] = cyc[2] ? crc[i] : crc[63-i];
|
||||
endgenerate
|
||||
|
||||
// Things not to merge
|
||||
always @(posedge clk) begin
|
||||
reg x;
|
||||
reg y;
|
||||
reg z;
|
||||
reg w;
|
||||
|
||||
// Do not merge if condition appears in an LVALUE
|
||||
x = crc[0];
|
||||
y = x ? crc[2] : crc[1];
|
||||
x = x ? crc[3] : crc[4];
|
||||
x = x ? crc[5] : crc[6];
|
||||
|
||||
`check(x, (crc[0] ? crc[3] : crc[4]) ? crc[5] : crc[6]);
|
||||
`check(y, crc[0] ? crc[2] : crc[1]);
|
||||
|
||||
// Do not merge if condition is not a pure expression
|
||||
$c("int _cnt = 0;");
|
||||
x = $c("_cnt++") ? crc[0] : crc[1];
|
||||
y = $c("_cnt++") ? crc[2] : crc[3];
|
||||
z = $c("_cnt++") ? crc[4] : crc[5];
|
||||
w = $c("_cnt++") ? crc[6] : crc[7];
|
||||
$c("if (_cnt != 4) abort();");
|
||||
|
||||
`check(x, crc[1]);
|
||||
`check(y, crc[2]);
|
||||
`check(z, crc[4]);
|
||||
`check(w, crc[6]);
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue