43 lines
1.1 KiB
C++
43 lines
1.1 KiB
C++
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include <fstream>
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#include VM_PREFIX_INCLUDE
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unsigned long long main_time = 0;
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double sc_time_stamp() { return main_time; }
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int main(int argc, char** argv) {
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Verilated::debug(0);
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Verilated::commandArgs(argc, argv);
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std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"top"}};
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std::ofstream logFile("obj_vlt/t_instrumentation/simulation_output.log");
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if (!logFile.is_open()) {
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printf("Error: Could not open log file\n");
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return 1;
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}
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while (main_time <= 100) {
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top->eval();
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logFile << "$time: " << main_time << " | "
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<< "Output outa: " << static_cast<int>(top->outa) << " | "
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<< "Output outb: " << static_cast<int>(top->outb) << std::endl;
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++main_time;
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}
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top->final();
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top.reset();
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printf("*-* All Finished *-*\n");
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return 0;
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}
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