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verilator/test_regress/t/t_assert_unique_case_bad.out

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Improve assertion for unique case (#4892) - Use parallel_case, unique, and unique0 in error message - Distinguish multiple match and no match - Show the case value that triggers the assertion
2024-02-13 13:53:32 +01:00
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Improve message for priority case assertion failure (#4905)
2024-02-22 09:09:14 +01:00
[90] %Error: t_assert_unique_case_bad.v:38: Assertion failed in top.t: unique case, but multiple matches found for '12'h388'
%Error: t/t_assert_unique_case_bad.v:38: Verilog $stop
Improve assertion for unique case (#4892) - Use parallel_case, unique, and unique0 in error message - Distinguish multiple match and no match - Show the case value that triggers the assertion
2024-02-13 13:53:32 +01:00
Aborting...