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// DESCRIPTION: Verilator: Verilog Test module
//
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// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2022 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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int x = 0 ;
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module t ;
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int a ;
int b ;
int i ;
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int arr [ 5 ] ;
// function with side effects
function int foo ( ) ;
x + = 1 ;
return 1 ;
endfunction ;
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// verilator lint_off ASSIGNEQEXPR
initial begin
a = 10 ;
i = ( a = 2 ) ;
`checkd ( a , 2 ) ;
`checkd ( i , 2 ) ;
a = 10 ;
i = ( a + = 2 ) ;
`checkd ( a , 12 ) ;
`checkd ( i , 12 ) ;
a = 10 ;
i = ( a - = 2 ) ;
`checkd ( a , 8 ) ;
`checkd ( i , 8 ) ;
a = 10 ;
i = ( a * = 2 ) ;
`checkd ( a , 20 ) ;
`checkd ( i , 20 ) ;
a = 10 ;
i = ( a / = 2 ) ;
`checkd ( a , 5 ) ;
`checkd ( i , 5 ) ;
a = 11 ;
i = ( a % = 2 ) ;
`checkd ( a , 1 ) ;
`checkd ( i , 1 ) ;
a = 10 ;
i = ( a & = 2 ) ;
`checkd ( a , 2 ) ;
`checkd ( i , 2 ) ;
a = 8 ;
i = ( a | = 2 ) ;
`checkd ( a , 10 ) ;
`checkd ( i , 10 ) ;
a = 10 ;
i = ( a ^ = 2 ) ;
`checkd ( a , 8 ) ;
`checkd ( i , 8 ) ;
a = 10 ;
i = ( a < < = 2 ) ;
`checkd ( a , 40 ) ;
`checkd ( i , 40 ) ;
a = 10 ;
i = ( a > > = 2 ) ;
`checkd ( a , 2 ) ;
`checkd ( i , 2 ) ;
a = 10 ;
i = ( a > > > = 2 ) ;
`checkd ( a , 2 ) ;
`checkd ( i , 2 ) ;
a = 10 ;
i = ( a = ( b = 5 ) ) ;
`checkd ( a , 5 ) ;
`checkd ( i , 5 ) ;
`checkd ( b , 5 ) ;
a = 10 ;
b = 6 ;
i = ( ( a + = ( b + = 1 ) + 1 ) ) ;
`checkd ( a , 18 ) ;
`checkd ( i , 18 ) ;
`checkd ( b , 7 ) ;
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arr [ 0 ] = 3 ;
arr [ 0 ] + = 4 ;
`checkd ( arr [ 0 ] , 7 ) ;
arr [ foo ( ) ] = 1 ;
`checkd ( x , 1 ) ;
arr [ foo ( ) ] + = 2 ;
`checkd ( arr [ 1 ] , 3 ) ;
`checkd ( x , 2 ) ;
arr [ foo ( ) + 1 ] = 6 ;
`checkd ( x , 3 ) ;
arr [ foo ( ) + 1 ] - = 5 ;
`checkd ( arr [ 2 ] , 1 ) ;
`checkd ( x , 4 ) ;
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i = 0 ;
arr [ i + + ] - = 2 ;
`checkd ( arr [ 0 ] , 5 ) ;
arr [ + + i ] + = 5 ;
`checkd ( arr [ 2 ] , 6 ) ;
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$write ( " *-* All Finished *-* \n " ) ;
$finish ;
end
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endmodule