43 lines
1.3 KiB
Systemverilog
43 lines
1.3 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// A class type parameter whose default reads $bits of a sibling type
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// parameter must not freeze that sibling at its default width when other
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// parameters of the interface are overridden (#7711).
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class cls #(int width);
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endclass
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interface ifc
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#(parameter int width = 8,
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parameter type dtype = logic[width-1:0],
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parameter type cparam = cls#($bits(dtype)));
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dtype data;
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endinterface
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module t;
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// width is overridden, dtype keeps its default logic[width-1:0], and the
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// class type parameter is overridden. dtype must follow width (1 bit).
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ifc #(.width(1), .cparam(cls#(1))) inst1();
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// Same interface left at its default width (8 bits) must still work.
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ifc inst8();
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always_comb inst1.data = 1'b0;
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initial begin
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if ($bits(inst1.data) != 1) begin
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$write("%%Error: $bits(inst1.data)=%0d exp=1\n", $bits(inst1.data));
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$stop;
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end
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if ($bits(inst8.data) != 8) begin
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$write("%%Error: $bits(inst8.data)=%0d exp=8\n", $bits(inst8.data));
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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