2024-09-08 19:00:03 +02:00
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#!/usr/bin/env python3
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2020-09-22 15:09:10 +02:00
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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2024-09-08 19:00:03 +02:00
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# Copyright 2024 by Wilson Snyder. This program is free software; you can
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2020-09-22 15:09:10 +02:00
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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2023-01-21 02:42:30 +01:00
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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2020-09-22 15:09:10 +02:00
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2024-09-08 19:00:03 +02:00
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import vltest_bootstrap
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2020-09-22 15:09:10 +02:00
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2024-09-08 19:00:03 +02:00
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test.scenarios('vlt_all')
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2020-09-22 15:09:10 +02:00
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2025-04-05 16:46:39 +02:00
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test.compile(verilator_flags2=['--cc --trace-vcd'])
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2020-09-22 15:09:10 +02:00
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2024-09-08 19:00:03 +02:00
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test.execute(fails=True)
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test.vcd_identical(test.trace_filename, test.golden_filename)
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test.passes()
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