verilator/docs/gen/ex_PROCASSINIT_faulty.rst

.. comment: generated by t_lint_procassinit_bad
.. code-block:: sv
   :linenos:
   :emphasize-lines: 1,5

     logic flop_out = 1;  // <--- Warning

     always @(posedge clk, negedge reset_l) begin
       if (enable) begin
         flop_out <= ~in;  // <--- Use of initialized
       end
     end