mirror of https://github.com/zachjs/sv2v.git
22 lines
851 B
Markdown
22 lines
851 B
Markdown
# relong Tests
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These tests are borrowed from Reid Long's [HDL Examples
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repository](https://bitbucket.org/ReidLong/hdl-examples). That repository was
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intended to provide examples for how the conversions in this project could be
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done.
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The `inline_concat` files were modified to remove a stray trailing semicolon.
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`array.v` previously had a custom implementation of `$clog2`, which was removed.
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Each test case (say, "foo") is comprised of the following files:
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1. `foo.sv`: original SystemVerilog
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2. `foo.v`: hand-converted Verilog
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3. `foo_tb.v`: basic testbench exercising the given modules
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The SystemVerilog source file is converted to Verilog using sv2v, and then both
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the converted file and the reference Verilog are simulated using Icarus Verilog.
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This produces VCD files for each which are expected to match exactly, except for
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the timestamp.
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