sv2v/test/error/interface_param_mismatch_ex...

9 lines
237 B
Systemverilog

// pattern: parameter "P" in instance "intf" of "Interface" expects an expression, but was given type logic
interface Interface;
parameter P = 0;
logic [P-1:0] x;
endinterface
module top;
Interface #(logic) intf();
endmodule