mirror of https://github.com/zachjs/sv2v.git
22 lines
535 B
Verilog
22 lines
535 B
Verilog
module top;
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genvar g;
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localparam SOME_VAL = 3;
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generate
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if (1) begin : i
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wire x = 0;
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initial $display("Interface %d %d", x, SOME_VAL);
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for (g = 10; g < 15; g = g + 1) begin
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initial $display(g);
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end
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end
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endgenerate
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generate
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if (1) begin : m
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initial $display("Module %d", i.x);
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for (g = 0; g < 5; g = g + 1) begin
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initial $display(g);
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end
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end
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endgenerate
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endmodule
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