mirror of https://github.com/zachjs/sv2v.git
79 lines
1.4 KiB
Verilog
79 lines
1.4 KiB
Verilog
`define PRINT(name, val) \
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dummy``name = val; \
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$display(`"name %h %h %0d %0d`", \
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val, dummy``name, $bits(val), $bits(dummy``name));
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module top;
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reg [31:0] dummyA;
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reg [31:0] dummyB;
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reg [31:0] dummyC;
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reg [31:0] dummyD;
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reg [31:0] dummyE;
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reg dummyF;
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reg [0:0] dummyG;
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reg [3:0] dummyH;
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reg [31:0] dummyI;
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initial begin
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`PRINT(A, 0)
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`PRINT(A, 1)
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`PRINT(A, 2)
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`PRINT(B, 2)
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`PRINT(B, 1)
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`PRINT(B, 3)
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`PRINT(C, 20)
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`PRINT(C, 0)
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`PRINT(C, 19)
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`PRINT(D, 16)
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`PRINT(D, 17)
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`PRINT(D, 18)
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`PRINT(E, 0)
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`PRINT(E, 16)
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`PRINT(E, 17)
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`PRINT(E, 18)
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`PRINT(E, 2)
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`PRINT(E, 3)
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`PRINT(F, 1'b0)
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`PRINT(F, 1'b1)
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`PRINT(G, 1'b0)
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`PRINT(G, 1'b1)
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`PRINT(H, 4'b1)
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`PRINT(H, 4'b0)
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`PRINT(I, 'b0)
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`PRINT(I, 'b1)
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end
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parameter USE_J = 1;
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generate
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if (USE_J) begin
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reg [31:0] dummyJ;
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initial begin
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`PRINT(J, 0)
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`PRINT(J, 1)
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`PRINT(J, 2)
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end
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end
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else begin
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reg [31:0] dummyZ;
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initial begin
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`PRINT(Z, 0)
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`PRINT(Z, 1)
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`PRINT(Z, 2)
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end
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end
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endgenerate
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endmodule
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