mirror of https://github.com/zachjs/sv2v.git
38 lines
751 B
Verilog
38 lines
751 B
Verilog
module mod(input [5:0] x);
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initial #1 $display("%b %b %b", x[4+:2], x[2+:2], x[0+:2]);
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endmodule
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module top;
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reg [5:0] a;
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wire [5:0] b;
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always @(*) a = b;
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reg x;
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wire [5:0] c;
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wire [5:0] d;
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wire [5:0] e;
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wire [5:0] f;
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initial x = 0;
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assign c = x ? d : !x ? e : f;
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reg [5:0] l;
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reg [5:0] m;
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reg [5:0] n;
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initial begin
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x = 1;
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l = { 2'bXZ, 2'b01, 2'b10 };
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m = { 2'b01, 2'b10, 2'b11 };
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n = { 2'b10, 2'b00, 2'b10 };
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end
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mod mod(!x ? l : x ? m : n);
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generate
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if (1) begin : A
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wire [1:0] c [0:2];
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wire [5:0] d;
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end
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endgenerate
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assign A.d = 0;
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initial $display("%b %b", A.c[0], A.d[1:0]);
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endmodule
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