sv2v/test/basic/import_no_reorder.v

9 lines
156 B
Verilog

`define DUMP(x) initial $display(`"x: %0d %b`", $bits(x), x);
module top;
wire a;
wire [7:0] b, c;
`DUMP(a)
`DUMP(b)
`DUMP(c)
endmodule