mirror of https://github.com/zachjs/sv2v.git
9 lines
156 B
Verilog
9 lines
156 B
Verilog
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`define DUMP(x) initial $display(`"x: %0d %b`", $bits(x), x);
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module top;
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wire a;
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wire [7:0] b, c;
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`DUMP(a)
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`DUMP(b)
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`DUMP(c)
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endmodule
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