mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 09:28:12 +02:00
5 lines
82 B
Verilog
5 lines
82 B
Verilog
module top;
|
|
reg [2:0] s = 3'b110;
|
|
initial #1 $display("%b", s);
|
|
endmodule
|