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SystemVerilog to Verilog conversion
21 Commits 1 Branch 14 Tags 3.4 MiB
Haskell 48.1%
SystemVerilog 26.2%
Verilog 16.4%
Yacc 6.4%
Shell 2.5%
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Zachary Snow a3937a2719 fix preproccessing multi-line defines messing up line numbers 2019-02-17 14:39:33 -05:00
Data Basic build setup! 2019-02-08 01:09:33 -05:00
Language fix preproccessing multi-line defines messing up line numbers 2019-02-17 14:39:33 -05:00
.gitignore switch to using stack 2019-02-11 23:48:49 -05:00
LICENSE updated LICENSE to reflect fork 2019-02-08 16:51:20 -05:00
Makefile switch to using stack 2019-02-11 23:48:49 -05:00
Setup.hs Initial commit: fork of https://github.com/tomahawkins/verilog 2019-02-07 23:49:12 -05:00
stack.yaml switch to using stack 2019-02-11 23:48:49 -05:00
sv2v.cabal switch to using stack 2019-02-11 23:48:49 -05:00
sv2v.hs support for reduction ops, non-named/non-identifier module instantiation arguments, always @* 2019-02-10 17:47:11 -05:00