mirror of https://github.com/zachjs/sv2v.git
74 lines
2.2 KiB
Markdown
74 lines
2.2 KiB
Markdown
# sv2v: SystemVerilog to Verilog
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sv2v is a tool for converting synthesizable SystemVerilog into Verilog that is
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synthesizable by tools with more limited feature sets. This project is primarily
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focused on converting SystemVerilog into the subset of Verilog supported by
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[Yosys]. However, sv2v also has support for targeting the [limited subset of
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Verilog] supported by [VTR]. In the long term, we hope for sv2v to be more
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configurable and extensible so that it can be used with new and different
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toolchains and as Verilog support evolves.
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[Yosys]: http://www.clifford.at/yosys/
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[limited subset of Verilog]: https://docs.verilogtorouting.org/en/latest/odin/#verilog-synthesizable-keyword-support
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[VTR]: https://github.com/verilog-to-routing/vtr-verilog-to-routing
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## Installation
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### Pre-built binaries
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Given the infamy of Haskell's build system, we aim to release pre-built binaries
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and installation files. This has not been done yet.
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### Building from source
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You must have [Stack] installed to build sv2v.
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[Stack]: https://www.haskellstack.org/
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```
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git clone https://github.com/zachjs/sv2v
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cd sv2v
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stack setup
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make
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```
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This creates the executable at `./bin/sv2v`
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## Usage
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The interface for this tool has not yet been finalized. Currently, running `sv2v
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path/to/file.sv` will output the converted file to `stdout`.
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```
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sv2v [OPTIONS] [FILE]
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Common flags:
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-t --target=TARGET target sythesizer (yosys, vtr; defaults to yosys)
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-? --help Display help message
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```
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## VTR Support
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sv2v can target VTR by specifying `--target=vtr` on the command line. Note that
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VTR does not support `generate` blocks, and this tool is not capable of
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converting those at this time.
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## SystemVerilog Parser/AST
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This project contains a basic preprocessor, lexer, parser, and abstract syntax
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tree for a subset of synthesizable SystemVerilog. The parser is not extremely
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strict, and the AST allows for the representation of syntactically (and
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semantically) invalid Verilog. The goal is to be more general in the
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representation to enable more standardized and straightforward conversion
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procedures. This could be extended into an independent and more fully-featured
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parer if there is significant interest.
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## License
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See the LICENSE file for copyright and licensing information.
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