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13 lines
219 B
Systemverilog
13 lines
219 B
Systemverilog
module top;
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logic [1:0] a [3];
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logic [1:0] b [3];
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always_comb a = b;
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logic x;
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logic [1:0] c [3];
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logic [1:0] d [3];
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logic [1:0] e [3];
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initial x = 0;
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assign c = x ? d : e;
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endmodule
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