mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 01:18:10 +02:00
Zachary Snow
67466eaa60
- module instances with modport bindings are now inlined - support for modports in generate loops - support for generic interfaces - implied modport instance propagation - add error message for interface instances missing port list
17 lines
337 B
Verilog
17 lines
337 B
Verilog
module top;
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generate
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begin : i
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wire [3:0] x;
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reg [1:0] w;
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end
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endgenerate
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assign i.x = 4'b1001;
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initial i.w = 2'b10;
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initial begin
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$display("%b", i.x[3]);
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$display("%b", i.x[2]);
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$display("%b", i.x[1]);
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$display("%b", i.x[0]);
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end
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endmodule
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