mirror of
https://github.com/zachjs/sv2v.git
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- module instances with modport bindings are now inlined - support for modports in generate loops - support for generic interfaces - implied modport instance propagation - add error message for interface instances missing port list
13 lines
211 B
Verilog
13 lines
211 B
Verilog
module ModuleC;
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wire y;
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assign y = 1;
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initial $display("ModuleB %b", y);
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wire x;
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assign x = 0;
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initial $display("ModuleA %b", x);
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endmodule
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module top;
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ModuleC module_c();
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endmodule
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